A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs

Seunghyun Lim, Jimin Cheon, Youngcheol Chae, Wunki Jung, Dong Hun Lee, Minho Kwon, Kwisung Yoo, Seogheon Ham, Gunhee Han

Research output: Contribution to journalArticle

43 Citations (Scopus)

Abstract

This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13-μm 1P4M process with pixel pitch of 2.25 μm. The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are + 0.59/- 0.83 LSB and + 2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.

Original languageEnglish
Article number5771069
Pages (from-to)2073-2083
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume46
Issue number9
DOIs
Publication statusPublished - 2011 Sep 1

Fingerprint

Image sensors
Pixels
Telecommunication repeaters
Electric power utilization
Capacitors
Sensors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Lim, Seunghyun ; Cheon, Jimin ; Chae, Youngcheol ; Jung, Wunki ; Lee, Dong Hun ; Kwon, Minho ; Yoo, Kwisung ; Ham, Seogheon ; Han, Gunhee. / A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs. In: IEEE Journal of Solid-State Circuits. 2011 ; Vol. 46, No. 9. pp. 2073-2083.
@article{0e878db18cd9490399f647af23e3072a,
title = "A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs",
abstract = "This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13-μm 1P4M process with pixel pitch of 2.25 μm. The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are + 0.59/- 0.83 LSB and + 2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.",
author = "Seunghyun Lim and Jimin Cheon and Youngcheol Chae and Wunki Jung and Lee, {Dong Hun} and Minho Kwon and Kwisung Yoo and Seogheon Ham and Gunhee Han",
year = "2011",
month = "9",
day = "1",
doi = "10.1109/JSSC.2011.2144010",
language = "English",
volume = "46",
pages = "2073--2083",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs. / Lim, Seunghyun; Cheon, Jimin; Chae, Youngcheol; Jung, Wunki; Lee, Dong Hun; Kwon, Minho; Yoo, Kwisung; Ham, Seogheon; Han, Gunhee.

In: IEEE Journal of Solid-State Circuits, Vol. 46, No. 9, 5771069, 01.09.2011, p. 2073-2083.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A 240-frames/s 2.1-mpixel CMOS image sensor with column-shared cyclic ADCs

AU - Lim, Seunghyun

AU - Cheon, Jimin

AU - Chae, Youngcheol

AU - Jung, Wunki

AU - Lee, Dong Hun

AU - Kwon, Minho

AU - Yoo, Kwisung

AU - Ham, Seogheon

AU - Han, Gunhee

PY - 2011/9/1

Y1 - 2011/9/1

N2 - This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13-μm 1P4M process with pixel pitch of 2.25 μm. The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are + 0.59/- 0.83 LSB and + 2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.

AB - This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13-μm 1P4M process with pixel pitch of 2.25 μm. The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are + 0.59/- 0.83 LSB and + 2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.

UR - http://www.scopus.com/inward/record.url?scp=80052071218&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052071218&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2011.2144010

DO - 10.1109/JSSC.2011.2144010

M3 - Article

AN - SCOPUS:80052071218

VL - 46

SP - 2073

EP - 2083

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 9

M1 - 5771069

ER -