A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss with Adaptive 2-Tap Data DFE and 1-Tap Edge DFE

Jinhyung Lee, Kwanseo Park, Kwangho Lee, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

11 Citations (Scopus)

Abstract

This brief presents a 1.62-to-10-Gb/s receiver for next generation video interconnected with an adaptive decision-feedback equalizer (DFE). The adaptive DFE facilitates the best bit error rate (BER) performance for various losses of video cables. A differential-pair stage is added to the DFE for extending an effective DFE range, presetting a minimum data level, and calibrating a mismatch offset. Circuit techniques are proposed to relax timing constraints for the direct-feedback DFE architecture. A referenceless frequency acquisition is performed during a dedicated clock recovery phase. The measured BER at 10 Gb/s is lower than 10-12 with a 23-dB loss cable. The RMS jitter and the peak-to-peak jitter of a recovered clock are measured as 2.38 ps and 17.5 ps, respectively. The prototype chip is implemented in 65-nm CMOS technology and occupies an active area of 0.254 mm2. This receiver consumes 24.4 mW at 10 Gb/s, corresponding to the energy efficiency of 2.44 pJ/b, which is the lowest compared to other recently published video interface receivers.

Original languageEnglish
Article number8382190
Pages (from-to)1295-1299
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume65
Issue number10
DOIs
Publication statusPublished - 2018 Oct

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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