This brief presents a 2.5-28 Gb/s multi-standard transmitter with a two-step time-multiplexing driver. The proposed two-step time-multiplexing driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing the number of stacks compared with a 4-to-1 time-multiplexing driver. In addition, the proposed transmitter can enhance the bandwidth by avoiding the use of a 1-unit-interval (1-UI) pulse which is one of the main design challenges in high-speed transmitters. It also provides a controllable output swing and a 3-tap feed-forward equalization (FFE) by turning-on and-off the driver slices. The output impedance is calibrated by a background feedback loop, resulting in a good signal integrity. The prototype chip fabricated in a 65-nm CMOS technology consists of a four-channel transmitter and a global all-digital phase-locked loop (ADPLL). One channel of the transmitter with the ADPLL occupies an active area of 0.23 mm2 and consume 213 mW at 28 Gb/s.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2019 Dec|
Bibliographical noteFunding Information:
Manuscript received July 3, 2019; accepted October 17, 2019. Date of publication October 24, 2019; date of current version December 6, 2019. This work was supported by the SK Hynix. This brief was recommended by Associate Editor T. Onoye. (Corresponding author: Deog-Kyoon Jeong.) M.-C. Choi, M. Shim, H.-G. Ko, H. Ju, K. Park, H. Kim, and D.-K. Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the InterUniversity Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea (e-mail: email@example.com; firstname.lastname@example.org).
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering