A 2.5-28 Gb/s Multi-Standard Transmitter with Two-Step Time-Multiplexing Driver

Moon Chul Choi; Deog Kyoon Jeong; Sung Yong Cho; Minkyo Shim; Byungmin Kim; Han Gon Ko; Haram Ju; Kwanseo Park; Hyojun Kim; Kwandong Kim

doi:10.1109/TCSII.2019.2949173

A 2.5-28 Gb/s Multi-Standard Transmitter with Two-Step Time-Multiplexing Driver

Moon Chul Choi, Deog Kyoon Jeong, Sung Yong Cho, Minkyo Shim, Byungmin Kim, Han Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim

School of System & Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This brief presents a 2.5-28 Gb/s multi-standard transmitter with a two-step time-multiplexing driver. The proposed two-step time-multiplexing driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing the number of stacks compared with a 4-to-1 time-multiplexing driver. In addition, the proposed transmitter can enhance the bandwidth by avoiding the use of a 1-unit-interval (1-UI) pulse which is one of the main design challenges in high-speed transmitters. It also provides a controllable output swing and a 3-tap feed-forward equalization (FFE) by turning-on and-off the driver slices. The output impedance is calibrated by a background feedback loop, resulting in a good signal integrity. The prototype chip fabricated in a 65-nm CMOS technology consists of a four-channel transmitter and a global all-digital phase-locked loop (ADPLL). One channel of the transmitter with the ADPLL occupies an active area of 0.23 mm² and consume 213 mW at 28 Gb/s.

Original language	English
Article number	8882375
Pages (from-to)	1927-1931
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	66
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2019.2949173
Publication status	Published - 2019 Dec

Bibliographical note

Funding Information:
Manuscript received July 3, 2019; accepted October 17, 2019. Date of publication October 24, 2019; date of current version December 6, 2019. This work was supported by the SK Hynix. This brief was recommended by Associate Editor T. Onoye. (Corresponding author: Deog-Kyoon Jeong.) M.-C. Choi, M. Shim, H.-G. Ko, H. Ju, K. Park, H. Kim, and D.-K. Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the InterUniversity Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea (e-mail: mcchoi@isdl.snu.ac.kr; dkjeong@snu.ac.kr).

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2019.2949173

Cite this

@article{fad135806cb348b6b0d7220567c60cae,

title = "A 2.5-28 Gb/s Multi-Standard Transmitter with Two-Step Time-Multiplexing Driver",

abstract = "This brief presents a 2.5-28 Gb/s multi-standard transmitter with a two-step time-multiplexing driver. The proposed two-step time-multiplexing driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing the number of stacks compared with a 4-to-1 time-multiplexing driver. In addition, the proposed transmitter can enhance the bandwidth by avoiding the use of a 1-unit-interval (1-UI) pulse which is one of the main design challenges in high-speed transmitters. It also provides a controllable output swing and a 3-tap feed-forward equalization (FFE) by turning-on and-off the driver slices. The output impedance is calibrated by a background feedback loop, resulting in a good signal integrity. The prototype chip fabricated in a 65-nm CMOS technology consists of a four-channel transmitter and a global all-digital phase-locked loop (ADPLL). One channel of the transmitter with the ADPLL occupies an active area of 0.23 mm2 and consume 213 mW at 28 Gb/s.",

author = "Choi, {Moon Chul} and Jeong, {Deog Kyoon} and Cho, {Sung Yong} and Minkyo Shim and Byungmin Kim and Ko, {Han Gon} and Haram Ju and Kwanseo Park and Hyojun Kim and Kwandong Kim",

note = "Funding Information: Manuscript received July 3, 2019; accepted October 17, 2019. Date of publication October 24, 2019; date of current version December 6, 2019. This work was supported by the SK Hynix. This brief was recommended by Associate Editor T. Onoye. (Corresponding author: Deog-Kyoon Jeong.) M.-C. Choi, M. Shim, H.-G. Ko, H. Ju, K. Park, H. Kim, and D.-K. Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the InterUniversity Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea (e-mail: mcchoi@isdl.snu.ac.kr; dkjeong@snu.ac.kr). Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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A 2.5-28 Gb/s Multi-Standard Transmitter with Two-Step Time-Multiplexing Driver. / Choi, Moon Chul; Jeong, Deog Kyoon; Cho, Sung Yong; Shim, Minkyo; Kim, Byungmin; Ko, Han Gon; Ju, Haram; Park, Kwanseo; Kim, Hyojun; Kim, Kwandong.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, No. 12, 8882375, 12.2019, p. 1927-1931.

Research output: Contribution to journal › Article › peer-review

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AU - Choi, Moon Chul

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AU - Shim, Minkyo

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AU - Ko, Han Gon

AU - Ju, Haram

AU - Park, Kwanseo

AU - Kim, Hyojun

AU - Kim, Kwandong

N1 - Funding Information: Manuscript received July 3, 2019; accepted October 17, 2019. Date of publication October 24, 2019; date of current version December 6, 2019. This work was supported by the SK Hynix. This brief was recommended by Associate Editor T. Onoye. (Corresponding author: Deog-Kyoon Jeong.) M.-C. Choi, M. Shim, H.-G. Ko, H. Ju, K. Park, H. Kim, and D.-K. Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the InterUniversity Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea (e-mail: mcchoi@isdl.snu.ac.kr; dkjeong@snu.ac.kr). Publisher Copyright: © 2004-2012 IEEE.

PY - 2019/12

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N2 - This brief presents a 2.5-28 Gb/s multi-standard transmitter with a two-step time-multiplexing driver. The proposed two-step time-multiplexing driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing the number of stacks compared with a 4-to-1 time-multiplexing driver. In addition, the proposed transmitter can enhance the bandwidth by avoiding the use of a 1-unit-interval (1-UI) pulse which is one of the main design challenges in high-speed transmitters. It also provides a controllable output swing and a 3-tap feed-forward equalization (FFE) by turning-on and-off the driver slices. The output impedance is calibrated by a background feedback loop, resulting in a good signal integrity. The prototype chip fabricated in a 65-nm CMOS technology consists of a four-channel transmitter and a global all-digital phase-locked loop (ADPLL). One channel of the transmitter with the ADPLL occupies an active area of 0.23 mm2 and consume 213 mW at 28 Gb/s.

AB - This brief presents a 2.5-28 Gb/s multi-standard transmitter with a two-step time-multiplexing driver. The proposed two-step time-multiplexing driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing the number of stacks compared with a 4-to-1 time-multiplexing driver. In addition, the proposed transmitter can enhance the bandwidth by avoiding the use of a 1-unit-interval (1-UI) pulse which is one of the main design challenges in high-speed transmitters. It also provides a controllable output swing and a 3-tap feed-forward equalization (FFE) by turning-on and-off the driver slices. The output impedance is calibrated by a background feedback loop, resulting in a good signal integrity. The prototype chip fabricated in a 65-nm CMOS technology consists of a four-channel transmitter and a global all-digital phase-locked loop (ADPLL). One channel of the transmitter with the ADPLL occupies an active area of 0.23 mm2 and consume 213 mW at 28 Gb/s.

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ER -

A 2.5-28 Gb/s Multi-Standard Transmitter with Two-Step Time-Multiplexing Driver

Abstract

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