A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

Kwanseo Park; Woorham Bae; Deog Kyoon Jeong

doi:10.1109/CICC.2017.7993599

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

Kwanseo Park, Woorham Bae, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

A 7.5-to-11.1 Gb/s half-rate referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is proposed. Using the bang-bang phase-frequency detector with a direct up/dn control, the referenceless CDR is realized by a single-loop architecture which performs both phase and frequency acquisition in the same loop. The proposed frequency acquisition scheme achieves a wide capture range of 3.6 Gb/s and reduces cycle-slips. The proposed CDR is fabricated in 65-nm CMOS technology and occupies an active area of 0.04 mm². At the data rate of 10 Gb/s, the proposed CDR consumes 27.1 mW from 1.3-V supply.

Original language	English
Title of host publication	38th Annual Custom Integrated Circuits Conference
Subtitle of host publication	A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509051915
DOIs	https://doi.org/10.1109/CICC.2017.7993599
Publication status	Published - 2017 Jul 26
Event	38th Annual Custom Integrated Circuits Conference, CICC 2017 - Austin, United States Duration: 2017 Apr 30 → 2017 May 3

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2017-April
ISSN (Print)	0886-5930

Conference

Conference	38th Annual Custom Integrated Circuits Conference, CICC 2017
Country/Territory	United States
City	Austin
Period	17/4/30 → 17/5/3

Bibliographical note

Funding Information:
This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2012M3A6A6054191). The chip fabrication was supported by IC Design Education Center (IDEC).

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2017.7993599

Cite this

Park, K., Bae, W., & Jeong, D. K. (2017). A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. In 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017 [7993599] (Proceedings of the Custom Integrated Circuits Conference; Vol. 2017-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2017.7993599

Park, Kwanseo ; Bae, Woorham ; Jeong, Deog Kyoon. / A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings of the Custom Integrated Circuits Conference).

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abstract = "A 7.5-to-11.1 Gb/s half-rate referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is proposed. Using the bang-bang phase-frequency detector with a direct up/dn control, the referenceless CDR is realized by a single-loop architecture which performs both phase and frequency acquisition in the same loop. The proposed frequency acquisition scheme achieves a wide capture range of 3.6 Gb/s and reduces cycle-slips. The proposed CDR is fabricated in 65-nm CMOS technology and occupies an active area of 0.04 mm2. At the data rate of 10 Gb/s, the proposed CDR consumes 27.1 mW from 1.3-V supply.",

author = "Kwanseo Park and Woorham Bae and Jeong, {Deog Kyoon}",

note = "Funding Information: This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2012M3A6A6054191). The chip fabrication was supported by IC Design Education Center (IDEC). Publisher Copyright: {\textcopyright} 2017 IEEE.; 38th Annual Custom Integrated Circuits Conference, CICC 2017 ; Conference date: 30-04-2017 Through 03-05-2017",

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Park, K, Bae, W & Jeong, DK 2017, A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. in 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017., 7993599, Proceedings of the Custom Integrated Circuits Conference, vol. 2017-April, Institute of Electrical and Electronics Engineers Inc., 38th Annual Custom Integrated Circuits Conference, CICC 2017, Austin, United States, 17/4/30. https://doi.org/10.1109/CICC.2017.7993599

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. / Park, Kwanseo; Bae, Woorham; Jeong, Deog Kyoon.

38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7993599 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2017-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2012M3A6A6054191). The chip fabrication was supported by IC Design Education Center (IDEC). Publisher Copyright: © 2017 IEEE.

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N2 - A 7.5-to-11.1 Gb/s half-rate referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is proposed. Using the bang-bang phase-frequency detector with a direct up/dn control, the referenceless CDR is realized by a single-loop architecture which performs both phase and frequency acquisition in the same loop. The proposed frequency acquisition scheme achieves a wide capture range of 3.6 Gb/s and reduces cycle-slips. The proposed CDR is fabricated in 65-nm CMOS technology and occupies an active area of 0.04 mm2. At the data rate of 10 Gb/s, the proposed CDR consumes 27.1 mW from 1.3-V supply.

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Park K, Bae W, Jeong DK. A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. In 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7993599. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC.2017.7993599

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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Cite this