A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control

Kwanseo Park, Woorham Bae, Deog Kyoon Jeong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A 7.5-to-11.1 Gb/s half-rate referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is proposed. Using the bang-bang phase-frequency detector with a direct up/dn control, the referenceless CDR is realized by a single-loop architecture which performs both phase and frequency acquisition in the same loop. The proposed frequency acquisition scheme achieves a wide capture range of 3.6 Gb/s and reduces cycle-slips. The proposed CDR is fabricated in 65-nm CMOS technology and occupies an active area of 0.04 mm2. At the data rate of 10 Gb/s, the proposed CDR consumes 27.1 mW from 1.3-V supply.

Original languageEnglish
Title of host publication38th Annual Custom Integrated Circuits Conference
Subtitle of host publicationA Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509051915
DOIs
Publication statusPublished - 2017 Jul 26
Event38th Annual Custom Integrated Circuits Conference, CICC 2017 - Austin, United States
Duration: 2017 Apr 302017 May 3

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2017-April
ISSN (Print)0886-5930

Conference

Conference38th Annual Custom Integrated Circuits Conference, CICC 2017
Country/TerritoryUnited States
CityAustin
Period17/4/3017/5/3

Bibliographical note

Funding Information:
This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as Global Frontier Project (CISS-2012M3A6A6054191). The chip fabrication was supported by IC Design Education Center (IDEC).

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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