A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR

Taewoong Kim, Youngcheol Chae

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a buffer-embedded noise-shaping SAR ADC, which separates the capacitive DAC (CDAC) and the sampling capacitor (CS) placed at the input and output of input buffer. This compensates the nonlinearity of the input buffer and enables CS value to be reduced, thus leading to significant power saving. An energy efficient 2nd-order noise-shaping is realized using passive integrators with the CS and the mismatch of CDAC is mitigated by error shaping techniques. Implemented in a 65 nm CMOS process, the ADC achieved 73.8 dB SNDR, 77 dB DR, and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. It consumes only 2.13 mW including the input buffer.

Original languageEnglish
Title of host publication2019 IEEE Custom Integrated Circuits Conference, CICC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538693957
DOIs
Publication statusPublished - 2019 Apr
Event40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States
Duration: 2019 Apr 142019 Apr 17

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2019-April
ISSN (Print)0886-5930

Conference

Conference40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
CountryUnited States
CityAustin
Period19/4/1419/4/17

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Kim, T., & Chae, Y. (2019). A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR. In 2019 IEEE Custom Integrated Circuits Conference, CICC 2019 [8780230] (Proceedings of the Custom Integrated Circuits Conference; Vol. 2019-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2019.8780230