A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR

Taewoong Kim; Youngcheol Chae

doi:10.1109/CICC.2019.8780230

A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR

Taewoong Kim, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a buffer-embedded noise-shaping SAR ADC, which separates the capacitive DAC (CDAC) and the sampling capacitor (C_S) placed at the input and output of input buffer. This compensates the nonlinearity of the input buffer and enables C_S value to be reduced, thus leading to significant power saving. An energy efficient 2^nd-order noise-shaping is realized using passive integrators with the C_S and the mismatch of CDAC is mitigated by error shaping techniques. Implemented in a 65 nm CMOS process, the ADC achieved 73.8 dB SNDR, 77 dB DR, and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. It consumes only 2.13 mW including the input buffer.

Original language	English
Title of host publication	2019 IEEE Custom Integrated Circuits Conference, CICC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538693957
DOIs	https://doi.org/10.1109/CICC.2019.8780230
Publication status	Published - 2019 Apr
Event	40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States Duration: 2019 Apr 14 → 2019 Apr 17

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2019-April
ISSN (Print)	0886-5930

Conference

Conference	40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
Country	United States
City	Austin
Period	19/4/14 → 19/4/17

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2019.8780230

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Kim, T., & Chae, Y. (2019). A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR. In 2019 IEEE Custom Integrated Circuits Conference, CICC 2019 [8780230] (Proceedings of the Custom Integrated Circuits Conference; Vol. 2019-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2019.8780230

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title = "A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR",

abstract = "This paper presents a buffer-embedded noise-shaping SAR ADC, which separates the capacitive DAC (CDAC) and the sampling capacitor (CS) placed at the input and output of input buffer. This compensates the nonlinearity of the input buffer and enables CS value to be reduced, thus leading to significant power saving. An energy efficient 2nd-order noise-shaping is realized using passive integrators with the CS and the mismatch of CDAC is mitigated by error shaping techniques. Implemented in a 65 nm CMOS process, the ADC achieved 73.8 dB SNDR, 77 dB DR, and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. It consumes only 2.13 mW including the input buffer.",

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Kim, T & Chae, Y 2019, A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR. in 2019 IEEE Custom Integrated Circuits Conference, CICC 2019., 8780230, Proceedings of the Custom Integrated Circuits Conference, vol. 2019-April, Institute of Electrical and Electronics Engineers Inc., 40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, United States, 19/4/14. https://doi.org/10.1109/CICC.2019.8780230

A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR. / Kim, Taewoong; Chae, Youngcheol.

2019 IEEE Custom Integrated Circuits Conference, CICC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8780230 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2019-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper presents a buffer-embedded noise-shaping SAR ADC, which separates the capacitive DAC (CDAC) and the sampling capacitor (CS) placed at the input and output of input buffer. This compensates the nonlinearity of the input buffer and enables CS value to be reduced, thus leading to significant power saving. An energy efficient 2nd-order noise-shaping is realized using passive integrators with the CS and the mismatch of CDAC is mitigated by error shaping techniques. Implemented in a 65 nm CMOS process, the ADC achieved 73.8 dB SNDR, 77 dB DR, and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. It consumes only 2.13 mW including the input buffer.

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