This paper presents a buffer-embedded noise-shaping SAR ADC, which separates the capacitive DAC (CDAC) and the sampling capacitor (CS) placed at the input and output of input buffer. This compensates the nonlinearity of the input buffer and enables CS value to be reduced, thus leading to significant power saving. An energy efficient 2nd-order noise-shaping is realized using passive integrators with the CS and the mismatch of CDAC is mitigated by error shaping techniques. Implemented in a 65 nm CMOS process, the ADC achieved 73.8 dB SNDR, 77 dB DR, and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. It consumes only 2.13 mW including the input buffer.
|Title of host publication||2019 IEEE Custom Integrated Circuits Conference, CICC 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2019 Apr|
|Event||40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States|
Duration: 2019 Apr 14 → 2019 Apr 17
|Name||Proceedings of the Custom Integrated Circuits Conference|
|Conference||40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019|
|Period||19/4/14 → 19/4/17|
Bibliographical noteFunding Information:
This paper is supported by Future Interconnect Technology Cluster Program of Samsung Electronics.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering