A 3 dimensional built-in self-repair scheme for yield improvement of 3 dimensional memories

Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.

Original languageEnglish
Article number7061513
Pages (from-to)586-595
Number of pages10
JournalIEEE Transactions on Reliability
Volume64
Issue number2
DOIs
Publication statusPublished - 2015 Jun 1

Fingerprint

Repair
Data storage equipment
Redundancy
Random access storage

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

Cite this

Kang, Wooheon ; Lee, Changwook ; Lim, Hyunyul ; Kang, Sungho. / A 3 dimensional built-in self-repair scheme for yield improvement of 3 dimensional memories. In: IEEE Transactions on Reliability. 2015 ; Vol. 64, No. 2. pp. 586-595.
@article{0a2f00ec0444482da109f8e5a0abf8ba,
title = "A 3 dimensional built-in self-repair scheme for yield improvement of 3 dimensional memories",
abstract = "A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55{\%} of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.",
author = "Wooheon Kang and Changwook Lee and Hyunyul Lim and Sungho Kang",
year = "2015",
month = "6",
day = "1",
doi = "10.1109/TR.2015.2410274",
language = "English",
volume = "64",
pages = "586--595",
journal = "IEEE Transactions on Reliability",
issn = "0018-9529",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

A 3 dimensional built-in self-repair scheme for yield improvement of 3 dimensional memories. / Kang, Wooheon; Lee, Changwook; Lim, Hyunyul; Kang, Sungho.

In: IEEE Transactions on Reliability, Vol. 64, No. 2, 7061513, 01.06.2015, p. 586-595.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A 3 dimensional built-in self-repair scheme for yield improvement of 3 dimensional memories

AU - Kang, Wooheon

AU - Lee, Changwook

AU - Lim, Hyunyul

AU - Kang, Sungho

PY - 2015/6/1

Y1 - 2015/6/1

N2 - A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.

AB - A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.

UR - http://www.scopus.com/inward/record.url?scp=85027928266&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027928266&partnerID=8YFLogxK

U2 - 10.1109/TR.2015.2410274

DO - 10.1109/TR.2015.2410274

M3 - Article

VL - 64

SP - 586

EP - 595

JO - IEEE Transactions on Reliability

JF - IEEE Transactions on Reliability

SN - 0018-9529

IS - 2

M1 - 7061513

ER -