A 32-bit carry lookahead adder using dual-path All-N logic

Ge Yang, Seongook Jung, Kwang Hyun Baek, Soo Hwan Kim, Suki Kim, Sung Mo Kang

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-μm 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-μm CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

Original languageEnglish
Pages (from-to)992-996
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume13
Issue number8
DOIs
Publication statusPublished - 2005 Aug 1

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Adders
Transistors
Capacitance
Silicon
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yang, Ge ; Jung, Seongook ; Baek, Kwang Hyun ; Kim, Soo Hwan ; Kim, Suki ; Kang, Sung Mo. / A 32-bit carry lookahead adder using dual-path All-N logic. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005 ; Vol. 13, No. 8. pp. 992-996.
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A 32-bit carry lookahead adder using dual-path All-N logic. / Yang, Ge; Jung, Seongook; Baek, Kwang Hyun; Kim, Soo Hwan; Kim, Suki; Kang, Sung Mo.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 8, 01.08.2005, p. 992-996.

Research output: Contribution to journalArticle

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