A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

Dae Hyun Kwon, Minkyu Kim, Sung Geun Kim, Woo Young Choi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

We present a 32-Gb/s PAM-4 quarter-rate clock and data recovery (CDR) circuit having a newly proposed selective transition detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.

Original languageEnglish
Article number8410680
Pages (from-to)362-366
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume66
Issue number3
DOIs
Publication statusPublished - 2019 Mar

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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