A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit with an Input Slew-rate Tolerant Selective Transition Detector

Dae Hyun Kwon, Minkyu Kim, Sung Geun Kim, Woo-Young Choi

Research output: Contribution to journalArticle

Abstract

We present a 32-Gb/s PAM-4 quarter-rate Clock and Data Recovery (CDR) circuit having a newly proposed Selective Transition Detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
DOIs
Publication statusAccepted/In press - 2018 Jul 12

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Clock and data recovery circuits (CDR circuits)
Pulse amplitude modulation
Clocks
Detectors
Recovery
Logic gates
Jitter
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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title = "A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit with an Input Slew-rate Tolerant Selective Transition Detector",
abstract = "We present a 32-Gb/s PAM-4 quarter-rate Clock and Data Recovery (CDR) circuit having a newly proposed Selective Transition Detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.",
author = "Kwon, {Dae Hyun} and Minkyu Kim and Kim, {Sung Geun} and Woo-Young Choi",
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T1 - A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit with an Input Slew-rate Tolerant Selective Transition Detector

AU - Kwon, Dae Hyun

AU - Kim, Minkyu

AU - Kim, Sung Geun

AU - Choi, Woo-Young

PY - 2018/7/12

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N2 - We present a 32-Gb/s PAM-4 quarter-rate Clock and Data Recovery (CDR) circuit having a newly proposed Selective Transition Detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.

AB - We present a 32-Gb/s PAM-4 quarter-rate Clock and Data Recovery (CDR) circuit having a newly proposed Selective Transition Detector (STD). The STD allows phase detection of PAM-4 data in a simple manner by eliminating middle transition and majority voting with simple logic gates. In addition, using the edge-rotating technique with quarter-rate CDR operation, our CDR achieves power consumption and chip area reduction. A prototype 32-Gb/s quarter-rate PAM-4 CDR circuit is realized with 28-nm CMOS technology. The CDR circuit consumes 32 mW with 1.2-V supply and the recovered clock signal has 0.0136-UI rms jitter.

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