A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector

Ki Hyun Pyun, Dae Hyun Kwon, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm2, both of which are much less than those of conventional multi-rate CDR circuits.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages327-329
Number of pages3
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 252016 Oct 28

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16/10/2516/10/28

Fingerprint

Clock and data recovery circuits (CDR circuits)
Detectors
Variable frequency oscillators
Energy efficiency
Clocks
Recovery

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing

Cite this

Pyun, K. H., Kwon, D. H., & Choi, W. Y. (2017). A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 327-329). [7803966] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7803966
Pyun, Ki Hyun ; Kwon, Dae Hyun ; Choi, Woo Young. / A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 327-329
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abstract = "A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm2, both of which are much less than those of conventional multi-rate CDR circuits.",
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Pyun, KH, Kwon, DH & Choi, WY 2017, A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7803966, Institute of Electrical and Electronics Engineers Inc., pp. 327-329, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 16/10/25. https://doi.org/10.1109/APCCAS.2016.7803966

A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. / Pyun, Ki Hyun; Kwon, Dae Hyun; Choi, Woo Young.

2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 327-329 7803966.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Pyun KH, Kwon DH, Choi WY. A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 327-329. 7803966 https://doi.org/10.1109/APCCAS.2016.7803966