We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW\ channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98× 108 or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.
|Number of pages||11|
|Journal||IEEE Transactions on Biomedical Circuits and Systems|
|Publication status||Published - 2012|
Bibliographical noteFunding Information:
Manuscript received January 31, 2012; revised April 23, 2012; accepted September 03, 2012. Date of publication October 18, 2012; date of current version November 28, 2012. This work was supported in part by NSF grant EECS-0925441. This paper was recommended by Associate Editor T. Con-standinou.
All Science Journal Classification (ASJC) codes
- Biomedical Engineering
- Electrical and Electronic Engineering