A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit with Unlimited Frequency Acquisition Capability in 65-nm CMOS

Kwanseo Park, Kwangho Lee, Sung Yong Cho, Jinhyung Lee, Jeongho Hwang, Min Seong Choo, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)

Abstract

A continuous-rate referenceless clock and data recovery (CDR) circuit with an unlimited frequency acquisition capability is presented. The proposed frequency detector (FD) is derived from a multi-phase oversampling FD. Through accurate analysis of the root causes limiting the capture range, the extension techniques are proposed and digitally implemented by a small hardware overhead. The FD achieves the unlimited frequency detection capability and exhibits robust operation regardless of the initial clock frequency. The effect of the quadrature error is analyzed and verified by simulation. In addition, a frequency lock detector is implemented to control the loop gain for fast frequency acquisition. The prototype CDR circuit was designed and fabricated in a 65-nm CMOS process, occupying an active area of 0.045 mm2. The CDR circuit achieves a capture range from 4 Gb/s to 20 Gb/s, which is limited only by the oscillator operating range. The worst case acquisition time is 25 mu text{s} with a PRBS31 pattern. The CDR circuit achieves a BER less than 10-12 and an energy efficiency of 1.87 pJ/b.

Original languageEnglish
Article number9239394
Pages (from-to)1597-1607
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume56
Issue number5
DOIs
Publication statusPublished - 2021 May

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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