A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR with Unlimited Frequency Detection Capability in 65nm CMOS

Kwanseo Park; Kwangho Lee; Sung Yong Cho; Jinhyung Lee; Jeongho Hwang; Min Seong Choo; Deog Kyoon Jeong

doi:10.23919/VLSIC.2019.8778157

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR with Unlimited Frequency Detection Capability in 65nm CMOS

Kwanseo Park, Kwangho Lee, Sung Yong Cho, Jinhyung Lee, Jeongho Hwang, Min Seong Choo, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme. The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is 25 μ s with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm².

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C194-C195
ISBN (Electronic)	9784863487185
DOIs	https://doi.org/10.23919/VLSIC.2019.8778157
Publication status	Published - 2019 Jun
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 2019 Jun 9 → 2019 Jun 14

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2019-June

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/Territory	Japan
City	Kyoto
Period	19/6/9 → 19/6/14

Bibliographical note

Publisher Copyright:
© 2019 JSAP.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.23919/VLSIC.2019.8778157

Cite this

Park, K., Lee, K., Cho, S. Y., Lee, J., Hwang, J., Choo, M. S., & Jeong, D. K. (2019). A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR with Unlimited Frequency Detection Capability in 65nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C194-C195). [8778157] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2019.8778157

Park, Kwanseo ; Lee, Kwangho ; Cho, Sung Yong et al. / A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR with Unlimited Frequency Detection Capability in 65nm CMOS. 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. pp. C194-C195 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme. The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is 25 μ s with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm2.",

author = "Kwanseo Park and Kwangho Lee and Cho, {Sung Yong} and Jinhyung Lee and Jeongho Hwang and Choo, {Min Seong} and Jeong, {Deog Kyoon}",

note = "Publisher Copyright: {\textcopyright} 2019 JSAP.; 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

year = "2019",

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language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

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Park, K, Lee, K, Cho, SY, Lee, J, Hwang, J, Choo, MS & Jeong, DK 2019, A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR with Unlimited Frequency Detection Capability in 65nm CMOS. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8778157, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. C194-C195, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 19/6/9. https://doi.org/10.23919/VLSIC.2019.8778157

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR with Unlimited Frequency Detection Capability in 65nm CMOS. / Park, Kwanseo; Lee, Kwangho; Cho, Sung Yong et al.

2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. C194-C195 8778157 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme. The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is 25 μ s with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm2.

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Park K, Lee K, Cho SY, Lee J, Hwang J, Choo MS et al. A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR with Unlimited Frequency Detection Capability in 65nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. C194-C195. 8778157. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2019.8778157

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR with Unlimited Frequency Detection Capability in 65nm CMOS

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

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