This paper presents a referenceless digital clock and data recovery (CDR) with an unlimited frequency detection capability that is extended from a multi-phase oversampling scheme. The CDR achieves a capture range from 4Gb/s to 20Gb/s, which is limited only by the operating frequency of the oscillator. Frequency acquisition is possible at any initial frequency and the worst-case acquisition time is 25 μ s with a PRBS31 pattern. The CDR fabricated in 65nm CMOS consumes 37.3mW at 20Gb/s and occupies 0.045mm2.
|Title of host publication||2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2019 Jun|
|Event||33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan|
Duration: 2019 Jun 9 → 2019 Jun 14
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||33rd Symposium on VLSI Circuits, VLSI Circuits 2019|
|Period||19/6/9 → 19/6/14|
Bibliographical notePublisher Copyright:
© 2019 JSAP.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering