The amplifiers used to improve the noise performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlinearity can be improved by analog or digital techniques. Residue amplifiers used in pipelined ADCs have been improved to dissipate low power, preserving their linearity. Traditionally, closed-loop amplifiers with high open loop-gain are used for the residue amplifiers , but they require static current, thus degrading power efficiency. To improve the power efficiency of the residue amplifier, dynamic amplifiers have been investigated , , which allow using only the required bandwidth, thus minimizing the power consumption for a given noise requirement. However, a dynamic amplifier requires digital calibration to compensate for the nonlinearity, increasing the design complexity and limiting the robustness to PVT variations , .
|Title of host publication||2020 IEEE International Solid-State Circuits Conference, ISSCC 2020|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||3|
|Publication status||Published - 2020 Feb|
|Event||2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 - San Francisco, United States|
Duration: 2020 Feb 16 → 2020 Feb 20
|Name||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Conference||2020 IEEE International Solid-State Circuits Conference, ISSCC 2020|
|Period||20/2/16 → 20/2/20|
Bibliographical noteFunding Information:
This work is supported by the Future Interconnect Technology Cluster Program of Samsung Electronics.
© 2020 IEEE.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering