We demonstrate a low-power wireline transmitter with 2-tap pre-emphasis in which serialization is achieved by toggling serializer with data transition information extracted from parallel input data. This novel technique of serialization provides significantly reduced power consumption since it does not need the short pulse generation block required in the conventional serializer. In addition, the same data transition information can be directly used for implementing 2-tap pre-emphasize and, consequently, the need for the additional serializer required in the conventional pre-emphasis circuits can be eliminated, resulting in further reduced power consumption. A prototype transmitter realized in 65nm CMOS technology achieves energy efficiencies of 0.202 pJ/bit at 5 Gb/s and 0.3 pJ/bit at 8 Gb/s for 150 mVpp,d output voltage swing without pre-emphasis, and 0.252 pJ/bit at 5 Gb/s and 0.333 pJ/bit at 8 Gb/s with 2-tap pre-emphasis providing 6-dB equalization gain. To the best of our knowledge, these are the lowest energy efficiencies achieved for wireline transmitters realized in 65nm CMOS technology.
|Title of host publication||2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2017 Feb 6|
|Event||12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Toyama, Japan|
Duration: 2016 Nov 7 → 2016 Nov 9
|Name||2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings|
|Other||12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016|
|Period||16/11/7 → 16/11/9|
Bibliographical noteFunding Information:
This work was supported by Samsung Electronics and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) [2015R1A2A2A01007772]. The authors would like to thank the IC Design Education Center for chip fabrication and EDA software support.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Hardware and Architecture