A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier

Hyunchul Yoon; Teawoong Kim; Yigi Kwon; Youngcheol Chae

doi:10.1109/VLSITechnologyandCir46769.2022.9830300

A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier

Hyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a capacitively degenerated two-stage dynamic amplifier that achieves high voltage gain and good linearity in a residue amplifier of a pipelined SAR ADC. It uses an open-loop dynamic amplifier that exploits a capacitive degeneration, and its limited voltage gain is improved to 16× by using a two-stage configuration. Since the optimal timing of the voltage gain to achieve high linearity can be set with a simple timing generator, the error due to incomplete settling of the residue amplifier can be maintained with negligible power overhead. Fabricated in a 65-nm CMOS process, the pipelined SAR ADC achieves 65-dB SNDR and 79.8-dB SFDR at a sampling rate of 50 MS/s, while consuming only 0.46 mW. This corresponds to a Walden FoM of 6.33 fJ/conv.-step and a Schreier FoM of 172.35 dB.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	88-89
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830300
Publication status	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 2022 Jun 12 → 2022 Jun 17

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	22/6/12 → 22/6/17

Bibliographical note

Funding Information:
This work is supported by Samsung Electronics.

Publisher Copyright:
© 2022 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/VLSITechnologyandCir46769.2022.9830300

Cite this

Yoon, H., Kim, T., Kwon, Y., & Chae, Y. (2022). A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 88-89). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830300

Yoon, Hyunchul ; Kim, Teawoong ; Kwon, Yigi et al. / A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 88-89 (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier",

abstract = "This paper presents a capacitively degenerated two-stage dynamic amplifier that achieves high voltage gain and good linearity in a residue amplifier of a pipelined SAR ADC. It uses an open-loop dynamic amplifier that exploits a capacitive degeneration, and its limited voltage gain is improved to 16× by using a two-stage configuration. Since the optimal timing of the voltage gain to achieve high linearity can be set with a simple timing generator, the error due to incomplete settling of the residue amplifier can be maintained with negligible power overhead. Fabricated in a 65-nm CMOS process, the pipelined SAR ADC achieves 65-dB SNDR and 79.8-dB SFDR at a sampling rate of 50 MS/s, while consuming only 0.46 mW. This corresponds to a Walden FoM of 6.33 fJ/conv.-step and a Schreier FoM of 172.35 dB.",

author = "Hyunchul Yoon and Teawoong Kim and Yigi Kwon and Youngcheol Chae",

note = "Funding Information: This work is supported by Samsung Electronics. Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830300",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

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Yoon, H, Kim, T, Kwon, Y & Chae, Y 2022, A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, Institute of Electrical and Electronics Engineers Inc., pp. 88-89, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 22/6/12. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830300

A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. / Yoon, Hyunchul; Kim, Teawoong; Kwon, Yigi et al.

2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 88-89 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper presents a capacitively degenerated two-stage dynamic amplifier that achieves high voltage gain and good linearity in a residue amplifier of a pipelined SAR ADC. It uses an open-loop dynamic amplifier that exploits a capacitive degeneration, and its limited voltage gain is improved to 16× by using a two-stage configuration. Since the optimal timing of the voltage gain to achieve high linearity can be set with a simple timing generator, the error due to incomplete settling of the residue amplifier can be maintained with negligible power overhead. Fabricated in a 65-nm CMOS process, the pipelined SAR ADC achieves 65-dB SNDR and 79.8-dB SFDR at a sampling rate of 50 MS/s, while consuming only 0.46 mW. This corresponds to a Walden FoM of 6.33 fJ/conv.-step and a Schreier FoM of 172.35 dB.

AB - This paper presents a capacitively degenerated two-stage dynamic amplifier that achieves high voltage gain and good linearity in a residue amplifier of a pipelined SAR ADC. It uses an open-loop dynamic amplifier that exploits a capacitive degeneration, and its limited voltage gain is improved to 16× by using a two-stage configuration. Since the optimal timing of the voltage gain to achieve high linearity can be set with a simple timing generator, the error due to incomplete settling of the residue amplifier can be maintained with negligible power overhead. Fabricated in a 65-nm CMOS process, the pipelined SAR ADC achieves 65-dB SNDR and 79.8-dB SFDR at a sampling rate of 50 MS/s, while consuming only 0.46 mW. This corresponds to a Walden FoM of 6.33 fJ/conv.-step and a Schreier FoM of 172.35 dB.

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Yoon H, Kim T, Kwon Y, Chae Y. A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 88-89. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830300

A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

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