A 5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers

Hyunsoo Song; Sungjin Oh; Juan Salinas; Sung Yun Park; Euisik Yoon

A 5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers

Hyunsoo Song, Sungjin Oh, Juan Salinas, Sung Yun Park, Euisik Yoon

Yonsei Advanced Science Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We present a CMOS imager for low-latency face detection empowered by parallel imaging and computing of machine-learning (ML) classifiers. The energy-efficient parallel operation and multi-scale detection eliminate image capture delay and significantly alleviate backend computational loads. The proposed pixel architecture, composed of dynamic samplers in a global shutter (GS) pixel array, allows for energy-efficient in-memory charge-domain computing of feature extraction and classification. The illumination-invariant detection was realized by using log-Haar features. A prototype 240×240 imager achieved an on-chip face detection latency of 5.1ms with a 97.9% true positive rate and 2% false positive rate at 120fps. Moreover, a dynamic nature of in-memory computing allows an energy efficiency of 419pJ/pixel for feature extraction and classification, leading to the smallest latency-energy product of 3.66ms∙nJ/pixel with digital backend processing.

Original language	English
Title of host publication	2021 Symposium on VLSI Technology, VLSI Technology 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487802
Publication status	Published - 2021
Event	41st Symposium on VLSI Technology, VLSI Technology 2021 - Virtual, Online, Japan Duration: 2021 Jun 13 → 2021 Jun 19

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2021-June
ISSN (Print)	0743-1562

Conference

Conference	41st Symposium on VLSI Technology, VLSI Technology 2021
Country/Territory	Japan
City	Virtual, Online
Period	21/6/13 → 21/6/19

Bibliographical note

Publisher Copyright:
© 2021 JSAP

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Cite this

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title = "A 5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers",

abstract = "We present a CMOS imager for low-latency face detection empowered by parallel imaging and computing of machine-learning (ML) classifiers. The energy-efficient parallel operation and multi-scale detection eliminate image capture delay and significantly alleviate backend computational loads. The proposed pixel architecture, composed of dynamic samplers in a global shutter (GS) pixel array, allows for energy-efficient in-memory charge-domain computing of feature extraction and classification. The illumination-invariant detection was realized by using log-Haar features. A prototype 240×240 imager achieved an on-chip face detection latency of 5.1ms with a 97.9% true positive rate and 2% false positive rate at 120fps. Moreover, a dynamic nature of in-memory computing allows an energy efficiency of 419pJ/pixel for feature extraction and classification, leading to the smallest latency-energy product of 3.66ms∙nJ/pixel with digital backend processing.",

author = "Hyunsoo Song and Sungjin Oh and Juan Salinas and Park, {Sung Yun} and Euisik Yoon",

note = "Publisher Copyright: {\textcopyright} 2021 JSAP; 41st Symposium on VLSI Technology, VLSI Technology 2021 ; Conference date: 13-06-2021 Through 19-06-2021",

year = "2021",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 Symposium on VLSI Technology, VLSI Technology 2021",

address = "United States",

}

Song, H, Oh, S, Salinas, J, Park, SY & Yoon, E 2021, A 5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers. in 2021 Symposium on VLSI Technology, VLSI Technology 2021. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 41st Symposium on VLSI Technology, VLSI Technology 2021, Virtual, Online, Japan, 21/6/13.

A 5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers. / Song, Hyunsoo; Oh, Sungjin; Salinas, Juan et al.

2021 Symposium on VLSI Technology, VLSI Technology 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Park, Sung Yun

AU - Yoon, Euisik

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N2 - We present a CMOS imager for low-latency face detection empowered by parallel imaging and computing of machine-learning (ML) classifiers. The energy-efficient parallel operation and multi-scale detection eliminate image capture delay and significantly alleviate backend computational loads. The proposed pixel architecture, composed of dynamic samplers in a global shutter (GS) pixel array, allows for energy-efficient in-memory charge-domain computing of feature extraction and classification. The illumination-invariant detection was realized by using log-Haar features. A prototype 240×240 imager achieved an on-chip face detection latency of 5.1ms with a 97.9% true positive rate and 2% false positive rate at 120fps. Moreover, a dynamic nature of in-memory computing allows an energy efficiency of 419pJ/pixel for feature extraction and classification, leading to the smallest latency-energy product of 3.66ms∙nJ/pixel with digital backend processing.

AB - We present a CMOS imager for low-latency face detection empowered by parallel imaging and computing of machine-learning (ML) classifiers. The energy-efficient parallel operation and multi-scale detection eliminate image capture delay and significantly alleviate backend computational loads. The proposed pixel architecture, composed of dynamic samplers in a global shutter (GS) pixel array, allows for energy-efficient in-memory charge-domain computing of feature extraction and classification. The illumination-invariant detection was realized by using log-Haar features. A prototype 240×240 imager achieved an on-chip face detection latency of 5.1ms with a 97.9% true positive rate and 2% false positive rate at 120fps. Moreover, a dynamic nature of in-memory computing allows an energy efficiency of 419pJ/pixel for feature extraction and classification, leading to the smallest latency-energy product of 3.66ms∙nJ/pixel with digital backend processing.

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M3 - Conference contribution

AN - SCOPUS:85125467657

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2021 Symposium on VLSI Technology, VLSI Technology 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 41st Symposium on VLSI Technology, VLSI Technology 2021

Y2 - 13 June 2021 through 19 June 2021

ER -

A 5.1ms Low-Latency Face Detection Imager with In-Memory Charge-Domain Computing of Machine-Learning Classifiers

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

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Cite this