A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector with 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

Sangwoo Lee; Jinwoong Jeong; Taewoong Kim; Chanmin Park; Taewoo Kim; Youngcheol Chae

doi:10.1109/JSSC.2020.3011967

A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector with 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

Sangwoo Lee, Jinwoong Jeong, Taewoong Kim, Chanmin Park, Taewoo Kim, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

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Abstract

This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta-sigma ( Delta Sigma ) analog-to-digital converters (ADCs). The use of a CT incremental Delta Sigma ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45- mu text{m} pitch achieves a differential nonlinearity (DNL) of +0.79/-0.65 LSB, an integral nonlinearity (INL) of +6.85/-6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of 12.6mu text{s}. This detector achieves a CFPN of 181mu text {V}_{text {rms}} , a dark RN of 267mu text {V}_{text {rms}} , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves 3times larger spatial resolution, 1.8times higher pixel rate, 1.9times higher energy-efficiency, and 17 dB higher DR, simultaneously.

Original language	English
Article number	9162454
Pages (from-to)	2878-2888
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	55
Issue number	11
DOIs	https://doi.org/10.1109/JSSC.2020.3011967
Publication status	Published - 2020 Nov

Bibliographical note

Funding Information:
Manuscript received April 27, 2020; revised June 16, 2020; accepted July 15, 2020. Date of publication August 7, 2020; date of current version October 23, 2020. This article was approved by Associate Editor Pedram Mohseni. This work was supported by the Korea Medical Device Development Fund grant funded by the Korea Government (the Ministry of Science and ICT, the Ministry of Trade, Industry and Energy, the Ministry of Health & Welfare, South Korea, and the Ministry of Food and Drug Safety). (Corresponding author: Youngcheol Chae.) Sangwoo Lee, Taewoong Kim, Chanmin Park, and Youngcheol Chae are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: ychae@yonsei.ac.kr).

Publisher Copyright:
© 1966-2012 IEEE.

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Electrical and Electronic Engineering

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@article{f00e21a4ea6e47e5b1d4f287b69f3ee7,

title = "A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector with 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs",

abstract = "This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta-sigma ( Delta Sigma ) analog-to-digital converters (ADCs). The use of a CT incremental Delta Sigma ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45- mu text{m} pitch achieves a differential nonlinearity (DNL) of +0.79/-0.65 LSB, an integral nonlinearity (INL) of +6.85/-6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of 12.6mu text{s}. This detector achieves a CFPN of 181mu text {V}_{text {rms}} , a dark RN of 267mu text {V}_{text {rms}} , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves 3times larger spatial resolution, 1.8times higher pixel rate, 1.9times higher energy-efficiency, and 17 dB higher DR, simultaneously. ",

author = "Sangwoo Lee and Jinwoong Jeong and Taewoong Kim and Chanmin Park and Taewoo Kim and Youngcheol Chae",

note = "Funding Information: Manuscript received April 27, 2020; revised June 16, 2020; accepted July 15, 2020. Date of publication August 7, 2020; date of current version October 23, 2020. This article was approved by Associate Editor Pedram Mohseni. This work was supported by the Korea Medical Device Development Fund grant funded by the Korea Government (the Ministry of Science and ICT, the Ministry of Trade, Industry and Energy, the Ministry of Health & Welfare, South Korea, and the Ministry of Food and Drug Safety). (Corresponding author: Youngcheol Chae.) Sangwoo Lee, Taewoong Kim, Chanmin Park, and Youngcheol Chae are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: ychae@yonsei.ac.kr). Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

year = "2020",

month = nov,

doi = "10.1109/JSSC.2020.3011967",

language = "English",

volume = "55",

pages = "2878--2888",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector with 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

AU - Lee, Sangwoo

AU - Jeong, Jinwoong

AU - Kim, Taewoong

AU - Park, Chanmin

AU - Kim, Taewoo

AU - Chae, Youngcheol

N1 - Funding Information: Manuscript received April 27, 2020; revised June 16, 2020; accepted July 15, 2020. Date of publication August 7, 2020; date of current version October 23, 2020. This article was approved by Associate Editor Pedram Mohseni. This work was supported by the Korea Medical Device Development Fund grant funded by the Korea Government (the Ministry of Science and ICT, the Ministry of Trade, Industry and Energy, the Ministry of Health & Welfare, South Korea, and the Ministry of Food and Drug Safety). (Corresponding author: Youngcheol Chae.) Sangwoo Lee, Taewoong Kim, Chanmin Park, and Youngcheol Chae are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: ychae@yonsei.ac.kr). Publisher Copyright: © 1966-2012 IEEE.

PY - 2020/11

Y1 - 2020/11

N2 - This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta-sigma ( Delta Sigma ) analog-to-digital converters (ADCs). The use of a CT incremental Delta Sigma ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45- mu text{m} pitch achieves a differential nonlinearity (DNL) of +0.79/-0.65 LSB, an integral nonlinearity (INL) of +6.85/-6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of 12.6mu text{s}. This detector achieves a CFPN of 181mu text {V}_{text {rms}} , a dark RN of 267mu text {V}_{text {rms}} , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves 3times larger spatial resolution, 1.8times higher pixel rate, 1.9times higher energy-efficiency, and 17 dB higher DR, simultaneously.

AB - This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta-sigma ( Delta Sigma ) analog-to-digital converters (ADCs). The use of a CT incremental Delta Sigma ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45- mu text{m} pitch achieves a differential nonlinearity (DNL) of +0.79/-0.65 LSB, an integral nonlinearity (INL) of +6.85/-6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of 12.6mu text{s}. This detector achieves a CFPN of 181mu text {V}_{text {rms}} , a dark RN of 267mu text {V}_{text {rms}} , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves 3times larger spatial resolution, 1.8times higher pixel rate, 1.9times higher energy-efficiency, and 17 dB higher DR, simultaneously.

UR - http://www.scopus.com/inward/record.url?scp=85094930580&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85094930580&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2020.3011967

DO - 10.1109/JSSC.2020.3011967

M3 - Article

AN - SCOPUS:85094930580

VL - 55

SP - 2878

EP - 2888

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 11

M1 - 9162454

ER -

A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector with 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

Abstract

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