A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications

Kwisung Yoo, Gunhee Han, Sung Min Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-μm CMOS process, occupying the chip area of 0.025mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5mV pp, and the power consumption of only 5.2mW from a single 1.2-V power supply.

Original languageEnglish
Title of host publicationICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages537-540
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France
Duration: 2006 Dec 102006 Dec 13

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Other

OtherICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
CountryFrance
CityNice
Period06/12/1006/12/13

Fingerprint

Bandwidth
Negative resistance
Electric power utilization
Capacitance

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Yoo, K., Han, G., & Park, S. M. (2006). A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications. In ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems (pp. 537-540). [4263422] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2006.379844
Yoo, Kwisung ; Han, Gunhee ; Park, Sung Min. / A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications. ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems. 2006. pp. 537-540 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).
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abstract = "In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-μm CMOS process, occupying the chip area of 0.025mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5mV pp, and the power consumption of only 5.2mW from a single 1.2-V power supply.",
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Yoo, K, Han, G & Park, SM 2006, A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications. in ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems., 4263422, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 537-540, ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France, 06/12/10. https://doi.org/10.1109/ICECS.2006.379844

A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications. / Yoo, Kwisung; Han, Gunhee; Park, Sung Min.

ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems. 2006. p. 537-540 4263422 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-μm CMOS process, occupying the chip area of 0.025mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5mV pp, and the power consumption of only 5.2mW from a single 1.2-V power supply.

AB - In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-μm CMOS process, occupying the chip area of 0.025mm2. Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5mV pp, and the power consumption of only 5.2mW from a single 1.2-V power supply.

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Yoo K, Han G, Park SM. A 5.2-mW, 2.5-Gb/s limiting amplifer for OC-48 SONET applications. In ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems. 2006. p. 537-540. 4263422. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2006.379844