Abstract
We report a 5.28-Gb/s serializer ASIC for uncompressed long-haul video interconnects. Our ASIC is based on the serializer architecture which maintains the constant output data rate for various resolutions of incoming video signals from VGA to UXGA. With this, a wide-band phase-locked-loop in a serializer and a continuous-rate clock-and-data-recovery circuit in a de-serializer are not necessary. The serializer ASIC contains clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers. A VCSEL driver circuit is also integrated so that it can be used for long-haul transmission with multimode fiber. The ASIC produces 5.28-Gb/s serialized driving currents for VCSEL from parallel input signals. It occupies 3.45 mm 2 and consumes 151.7 mW.
| Original language | English |
|---|---|
| Pages (from-to) | 385-395 |
| Number of pages | 11 |
| Journal | Analog Integrated Circuits and Signal Processing |
| Volume | 73 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2012 Oct 1 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Hardware and Architecture
- Surfaces, Coatings and Films
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A 5.28-Gb/s serializer ASIC for uncompressed long-haul multimedia interconnects. / Park, Kang Yeob; Oh, Won Seok; Choi, Jong Chan; Choi, Woo Young.
In: Analog Integrated Circuits and Signal Processing, Vol. 73, No. 1, 01.10.2012, p. 385-395.Research output: Contribution to journal › Article
TY - JOUR
T1 - A 5.28-Gb/s serializer ASIC for uncompressed long-haul multimedia interconnects
AU - Park, Kang Yeob
AU - Oh, Won Seok
AU - Choi, Jong Chan
AU - Choi, Woo Young
PY - 2012/10/1
Y1 - 2012/10/1
N2 - We report a 5.28-Gb/s serializer ASIC for uncompressed long-haul video interconnects. Our ASIC is based on the serializer architecture which maintains the constant output data rate for various resolutions of incoming video signals from VGA to UXGA. With this, a wide-band phase-locked-loop in a serializer and a continuous-rate clock-and-data-recovery circuit in a de-serializer are not necessary. The serializer ASIC contains clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers. A VCSEL driver circuit is also integrated so that it can be used for long-haul transmission with multimode fiber. The ASIC produces 5.28-Gb/s serialized driving currents for VCSEL from parallel input signals. It occupies 3.45 mm 2 and consumes 151.7 mW.
AB - We report a 5.28-Gb/s serializer ASIC for uncompressed long-haul video interconnects. Our ASIC is based on the serializer architecture which maintains the constant output data rate for various resolutions of incoming video signals from VGA to UXGA. With this, a wide-band phase-locked-loop in a serializer and a continuous-rate clock-and-data-recovery circuit in a de-serializer are not necessary. The serializer ASIC contains clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers. A VCSEL driver circuit is also integrated so that it can be used for long-haul transmission with multimode fiber. The ASIC produces 5.28-Gb/s serialized driving currents for VCSEL from parallel input signals. It occupies 3.45 mm 2 and consumes 151.7 mW.
UR - http://www.scopus.com/inward/record.url?scp=84866742324&partnerID=8YFLogxK
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U2 - 10.1007/s10470-012-9899-3
DO - 10.1007/s10470-012-9899-3
M3 - Article
AN - SCOPUS:84866742324
VL - 73
SP - 385
EP - 395
JO - Analog Integrated Circuits and Signal Processing
JF - Analog Integrated Circuits and Signal Processing
SN - 0925-1030
IS - 1
ER -