A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms

Wang Soo Kim, Chang Kyung Seong, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

As the data rate requirements for many wireline applications increase, channel bandwidth limitation becomes a critical problem in serial interfaces. Equalizers are often used as a solution for this problem. In addition, many applications require the equalizer to be adaptive so that it can provide optimized equalization for different channel conditions. Various types of adaptive equalizers have been investigated for high-speed serial interface applications [1-6]. In the spectrum-balancing method, adaptive equalization is achieved by comparing high and low frequency components of signal power and generating feedback signals until the power spectrum is balanced [1]. Unfortunately, the precision of this scheme is easily affected by process variations, and capacitors both in filters and the feedback loop occupy a large Si area. Digital-signal processing based on maximum likelihood sequence detection can be used for adaptive equalization [2]. But, speed limitation and architecture complexity of ADC limits applicability of this scheme in high-speed applications. In the eye-opening monitoring (EOM) scheme, quality of the signal eye diagram is measured and used for equalizer adaptation [3-6]. For this method, a clock-recovery circuit is needed in order to generate clock signals synchronized to data for sampling. However, it can be difficult to recover clock signals from the initially closed eye diagram, limiting the applicability of this scheme. In this paper, we demonstrate an adaptive equalizer based on asynchronous-sampling histograms.

Original languageEnglish
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Pages358-359
Number of pages2
DOIs
Publication statusPublished - 2011 May 12
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: 2011 Feb 202011 Feb 24

Other

Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period11/2/2011/2/24

Fingerprint

Equalizers
Sampling
Clocks
Feedback
Power spectrum
Digital signal processing
Maximum likelihood
Capacitors
Bandwidth
Recovery
Networks (circuits)
Monitoring

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kim, W. S., Seong, C. K., & Choi, W. Y. (2011). A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011 (pp. 358-359). [5746353] https://doi.org/10.1109/ISSCC.2011.5746353
Kim, Wang Soo ; Seong, Chang Kyung ; Choi, Woo Young. / A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms. 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. 2011. pp. 358-359
@inproceedings{2ff00ac431824f438749af198af83f54,
title = "A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms",
abstract = "As the data rate requirements for many wireline applications increase, channel bandwidth limitation becomes a critical problem in serial interfaces. Equalizers are often used as a solution for this problem. In addition, many applications require the equalizer to be adaptive so that it can provide optimized equalization for different channel conditions. Various types of adaptive equalizers have been investigated for high-speed serial interface applications [1-6]. In the spectrum-balancing method, adaptive equalization is achieved by comparing high and low frequency components of signal power and generating feedback signals until the power spectrum is balanced [1]. Unfortunately, the precision of this scheme is easily affected by process variations, and capacitors both in filters and the feedback loop occupy a large Si area. Digital-signal processing based on maximum likelihood sequence detection can be used for adaptive equalization [2]. But, speed limitation and architecture complexity of ADC limits applicability of this scheme in high-speed applications. In the eye-opening monitoring (EOM) scheme, quality of the signal eye diagram is measured and used for equalizer adaptation [3-6]. For this method, a clock-recovery circuit is needed in order to generate clock signals synchronized to data for sampling. However, it can be difficult to recover clock signals from the initially closed eye diagram, limiting the applicability of this scheme. In this paper, we demonstrate an adaptive equalizer based on asynchronous-sampling histograms.",
author = "Kim, {Wang Soo} and Seong, {Chang Kyung} and Choi, {Woo Young}",
year = "2011",
month = "5",
day = "12",
doi = "10.1109/ISSCC.2011.5746353",
language = "English",
isbn = "9781612843001",
pages = "358--359",
booktitle = "2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011",

}

Kim, WS, Seong, CK & Choi, WY 2011, A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms. in 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011., 5746353, pp. 358-359, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, CA, United States, 11/2/20. https://doi.org/10.1109/ISSCC.2011.5746353

A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms. / Kim, Wang Soo; Seong, Chang Kyung; Choi, Woo Young.

2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. 2011. p. 358-359 5746353.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms

AU - Kim, Wang Soo

AU - Seong, Chang Kyung

AU - Choi, Woo Young

PY - 2011/5/12

Y1 - 2011/5/12

N2 - As the data rate requirements for many wireline applications increase, channel bandwidth limitation becomes a critical problem in serial interfaces. Equalizers are often used as a solution for this problem. In addition, many applications require the equalizer to be adaptive so that it can provide optimized equalization for different channel conditions. Various types of adaptive equalizers have been investigated for high-speed serial interface applications [1-6]. In the spectrum-balancing method, adaptive equalization is achieved by comparing high and low frequency components of signal power and generating feedback signals until the power spectrum is balanced [1]. Unfortunately, the precision of this scheme is easily affected by process variations, and capacitors both in filters and the feedback loop occupy a large Si area. Digital-signal processing based on maximum likelihood sequence detection can be used for adaptive equalization [2]. But, speed limitation and architecture complexity of ADC limits applicability of this scheme in high-speed applications. In the eye-opening monitoring (EOM) scheme, quality of the signal eye diagram is measured and used for equalizer adaptation [3-6]. For this method, a clock-recovery circuit is needed in order to generate clock signals synchronized to data for sampling. However, it can be difficult to recover clock signals from the initially closed eye diagram, limiting the applicability of this scheme. In this paper, we demonstrate an adaptive equalizer based on asynchronous-sampling histograms.

AB - As the data rate requirements for many wireline applications increase, channel bandwidth limitation becomes a critical problem in serial interfaces. Equalizers are often used as a solution for this problem. In addition, many applications require the equalizer to be adaptive so that it can provide optimized equalization for different channel conditions. Various types of adaptive equalizers have been investigated for high-speed serial interface applications [1-6]. In the spectrum-balancing method, adaptive equalization is achieved by comparing high and low frequency components of signal power and generating feedback signals until the power spectrum is balanced [1]. Unfortunately, the precision of this scheme is easily affected by process variations, and capacitors both in filters and the feedback loop occupy a large Si area. Digital-signal processing based on maximum likelihood sequence detection can be used for adaptive equalization [2]. But, speed limitation and architecture complexity of ADC limits applicability of this scheme in high-speed applications. In the eye-opening monitoring (EOM) scheme, quality of the signal eye diagram is measured and used for equalizer adaptation [3-6]. For this method, a clock-recovery circuit is needed in order to generate clock signals synchronized to data for sampling. However, it can be difficult to recover clock signals from the initially closed eye diagram, limiting the applicability of this scheme. In this paper, we demonstrate an adaptive equalizer based on asynchronous-sampling histograms.

UR - http://www.scopus.com/inward/record.url?scp=79955746506&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79955746506&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2011.5746353

DO - 10.1109/ISSCC.2011.5746353

M3 - Conference contribution

AN - SCOPUS:79955746506

SN - 9781612843001

SP - 358

EP - 359

BT - 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011

ER -

Kim WS, Seong CK, Choi WY. A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. 2011. p. 358-359. 5746353 https://doi.org/10.1109/ISSCC.2011.5746353