This paper presents a 3rd order single-bit CT ΔΣ modulator with active-RC integrators using negative-R assistant at virtual ground, which mitigates opamp's requirements including the thermal noise and linearity leading to a drastic power-saving. Fabricated in a 65nm CMOS process, the modulator occupies area of 0.27mm2. It achieves 100.5dB SFDR and 93.1dB DR in 20kHz BW, while consuming only 55μW from a 1.2V supply. This results in Schreier FoM of 178.7dB and Walden FoM of 63.1fJ/step.
|Title of host publication||2017 Symposium on VLSI Circuits, VLSI Circuits 2017|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2017 Aug 10|
|Event||31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan|
Duration: 2017 Jun 5 → 2017 Jun 8
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Other||31st Symposium on VLSI Circuits, VLSI Circuits 2017|
|Period||17/6/5 → 17/6/8|
Bibliographical notePublisher Copyright:
© 2017 JSAP.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering