A 5.5-mW +9.4-dBm IIP3 1.8-dB NF CMOS LNA employing multiple gated transistors with capacitance desensitization

Tae Hwan Jin, Tae Wook Kim

Research output: Contribution to journalArticlepeer-review

34 Citations (Scopus)

Abstract

A capacitance desensitization technique is proposed for a multiple gated transistors amplifier with source degeneration to relax second-order distortion contribution to a third-order intermodulation distortion (IMD3), as well as an induced-gate noise contribution to noise figure. An extra capacitance, which is added between gate and source nodes of input transistors in a parallel manner, can desensitize the contribution of second-order harmonic feedback to IMD3. The capacitance is useful for optimizing noise figure, as well by controlling the input matching network quality factor (Q), which can desensitize the induced-gate noise contribution to noise figure. The low-noise amplifier is implemented with the proposed technique using 1P6M 0.18- μm CMOS technology for 900-MHz code division multiple access (CDMA) receivers. It shows a third-order intercept point of +9.4 dBm and noise figure of 1.8 dB while consuming 5.5 mW at 1.5 V.

Original languageEnglish
Article number5560699
Pages (from-to)2529-2537
Number of pages9
JournalIEEE Transactions on Microwave Theory and Techniques
Volume58
Issue number10
DOIs
Publication statusPublished - 2010 Oct

Bibliographical note

Funding Information:
Manuscript received October 07, 2009; revised June 07, 2010; accepted June 30, 2010. Date of publication September 02, 2010; date of current version October 13, 2010. This work was supported by the Mid-career Researcher Program through a National Research Foundation (NRF) Grant funded by the Ministry of Education, Science and Technology (MEST) (2010-0012315).

All Science Journal Classification (ASJC) codes

  • Radiation
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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