Abstract
A capacitance desensitization technique is proposed for a multiple gated transistors amplifier with source degeneration to relax second-order distortion contribution to a third-order intermodulation distortion (IMD3), as well as an induced-gate noise contribution to noise figure. An extra capacitance, which is added between gate and source nodes of input transistors in a parallel manner, can desensitize the contribution of second-order harmonic feedback to IMD3. The capacitance is useful for optimizing noise figure, as well by controlling the input matching network quality factor (Q), which can desensitize the induced-gate noise contribution to noise figure. The low-noise amplifier is implemented with the proposed technique using 1P6M 0.18- μm CMOS technology for 900-MHz code division multiple access (CDMA) receivers. It shows a third-order intercept point of +9.4 dBm and noise figure of 1.8 dB while consuming 5.5 mW at 1.5 V.
| Original language | English |
|---|---|
| Article number | 5560699 |
| Pages (from-to) | 2529-2537 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Microwave Theory and Techniques |
| Volume | 58 |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 2010 Oct 1 |
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All Science Journal Classification (ASJC) codes
- Radiation
- Condensed Matter Physics
- Electrical and Electronic Engineering
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A 5.5-mW +9.4-dBm IIP3 1.8-dB NF CMOS LNA employing multiple gated transistors with capacitance desensitization. / Jin, Tae Hwan; Kim, tae wook.
In: IEEE Transactions on Microwave Theory and Techniques, Vol. 58, No. 10, 5560699, 01.10.2010, p. 2529-2537.Research output: Contribution to journal › Article
TY - JOUR
T1 - A 5.5-mW +9.4-dBm IIP3 1.8-dB NF CMOS LNA employing multiple gated transistors with capacitance desensitization
AU - Jin, Tae Hwan
AU - Kim, tae wook
PY - 2010/10/1
Y1 - 2010/10/1
N2 - A capacitance desensitization technique is proposed for a multiple gated transistors amplifier with source degeneration to relax second-order distortion contribution to a third-order intermodulation distortion (IMD3), as well as an induced-gate noise contribution to noise figure. An extra capacitance, which is added between gate and source nodes of input transistors in a parallel manner, can desensitize the contribution of second-order harmonic feedback to IMD3. The capacitance is useful for optimizing noise figure, as well by controlling the input matching network quality factor (Q), which can desensitize the induced-gate noise contribution to noise figure. The low-noise amplifier is implemented with the proposed technique using 1P6M 0.18- μm CMOS technology for 900-MHz code division multiple access (CDMA) receivers. It shows a third-order intercept point of +9.4 dBm and noise figure of 1.8 dB while consuming 5.5 mW at 1.5 V.
AB - A capacitance desensitization technique is proposed for a multiple gated transistors amplifier with source degeneration to relax second-order distortion contribution to a third-order intermodulation distortion (IMD3), as well as an induced-gate noise contribution to noise figure. An extra capacitance, which is added between gate and source nodes of input transistors in a parallel manner, can desensitize the contribution of second-order harmonic feedback to IMD3. The capacitance is useful for optimizing noise figure, as well by controlling the input matching network quality factor (Q), which can desensitize the induced-gate noise contribution to noise figure. The low-noise amplifier is implemented with the proposed technique using 1P6M 0.18- μm CMOS technology for 900-MHz code division multiple access (CDMA) receivers. It shows a third-order intercept point of +9.4 dBm and noise figure of 1.8 dB while consuming 5.5 mW at 1.5 V.
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U2 - 10.1109/TMTT.2010.2063790
DO - 10.1109/TMTT.2010.2063790
M3 - Article
AN - SCOPUS:77957992276
VL - 58
SP - 2529
EP - 2537
JO - IEEE Transactions on Microwave Theory and Techniques
JF - IEEE Transactions on Microwave Theory and Techniques
SN - 0018-9480
IS - 10
M1 - 5560699
ER -