A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS

Daesik Moon; Sangwoo Lee; Taewoong Kim; Woo Young Choi; Youngcheol Chae

doi:10.1109/A-SSCC56115.2022.9980652

A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS

Daesik Moon, Sangwoo Lee, Taewoong Kim, Woo Young Choi, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

As emerging applications require a high data-rate communication, ADCs for these systems should have a multi-GHz signal bandwidth [1]. Typically, a flash ADC is the most widely used structure for the GHz ADC thanks to 2N-1 comparators deployed in parallel for an N-bit operation. Flash ADCs usually adopt a track-and-hold (T/H) at the frontend to sample its high-speed inputs before the quantization, and thus the frontend T/H often limits the speed and resolution of the ADCs [1-4]. In addition, a dedicated time for the T/H should be compromised with comparators' operation time out of the given sampling period. This work presents a 6-bit 5.12 GS/s flash ADC with T/H-embedded dynamic preamplifier. Without having a dedicated T/H, the first preamplifiers sample the input signal at the output and then the amplified signal is transferred to the subsequent stage within one clock period in a pipeline fashion. The dynamic preamplifiers consist of two stages. Each preamplifier stage is interpolated by a factor of 2, thus resulting in 4× interpolated preamplifiers for 6-bit flash ADC. Consequently, the prototype ADC achieves an SNDR of 32.97dB and SFDR of 41.52dB at 5.12 GS/s.

Original language	English
Title of host publication	2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665471435
DOIs	https://doi.org/10.1109/A-SSCC56115.2022.9980652
Publication status	Published - 2022
Event	2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Taipei, Taiwan, Province of China Duration: 2022 Nov 6 → 2022 Nov 9

Publication series

Name	2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings

Conference

Conference	2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022
Country/Territory	Taiwan, Province of China
City	Taipei
Period	22/11/6 → 22/11/9

Bibliographical note

Funding Information:
This work was supported by Samsung Electronics

Publisher Copyright:
© 2022 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Signal Processing
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Instrumentation
Computer Networks and Communications

Access to Document

10.1109/A-SSCC56115.2022.9980652

Cite this

Moon, D., Lee, S., Kim, T., Choi, W. Y., & Chae, Y. (2022). A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS. In 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings (2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC56115.2022.9980652

@inproceedings{c81144c2f7d84d21befc1c1b4df4c3b4,

title = "A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS",

abstract = "As emerging applications require a high data-rate communication, ADCs for these systems should have a multi-GHz signal bandwidth [1]. Typically, a flash ADC is the most widely used structure for the GHz ADC thanks to 2N-1 comparators deployed in parallel for an N-bit operation. Flash ADCs usually adopt a track-and-hold (T/H) at the frontend to sample its high-speed inputs before the quantization, and thus the frontend T/H often limits the speed and resolution of the ADCs [1-4]. In addition, a dedicated time for the T/H should be compromised with comparators' operation time out of the given sampling period. This work presents a 6-bit 5.12 GS/s flash ADC with T/H-embedded dynamic preamplifier. Without having a dedicated T/H, the first preamplifiers sample the input signal at the output and then the amplified signal is transferred to the subsequent stage within one clock period in a pipeline fashion. The dynamic preamplifiers consist of two stages. Each preamplifier stage is interpolated by a factor of 2, thus resulting in 4× interpolated preamplifiers for 6-bit flash ADC. Consequently, the prototype ADC achieves an SNDR of 32.97dB and SFDR of 41.52dB at 5.12 GS/s.",

author = "Daesik Moon and Sangwoo Lee and Taewoong Kim and Choi, {Woo Young} and Youngcheol Chae",

note = "Funding Information: This work was supported by Samsung Electronics Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 ; Conference date: 06-11-2022 Through 09-11-2022",

year = "2022",

doi = "10.1109/A-SSCC56115.2022.9980652",

language = "English",

series = "2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings",

address = "United States",

}

Moon, D, Lee, S, Kim, T, Choi, WY & Chae, Y 2022, A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS. in 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings. 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022, Taipei, Taiwan, Province of China, 22/11/6. https://doi.org/10.1109/A-SSCC56115.2022.9980652

A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS. / Moon, Daesik; Lee, Sangwoo; Kim, Taewoong et al.

2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS

AU - Moon, Daesik

AU - Lee, Sangwoo

AU - Kim, Taewoong

AU - Choi, Woo Young

AU - Chae, Youngcheol

PY - 2022

Y1 - 2022

N2 - As emerging applications require a high data-rate communication, ADCs for these systems should have a multi-GHz signal bandwidth [1]. Typically, a flash ADC is the most widely used structure for the GHz ADC thanks to 2N-1 comparators deployed in parallel for an N-bit operation. Flash ADCs usually adopt a track-and-hold (T/H) at the frontend to sample its high-speed inputs before the quantization, and thus the frontend T/H often limits the speed and resolution of the ADCs [1-4]. In addition, a dedicated time for the T/H should be compromised with comparators' operation time out of the given sampling period. This work presents a 6-bit 5.12 GS/s flash ADC with T/H-embedded dynamic preamplifier. Without having a dedicated T/H, the first preamplifiers sample the input signal at the output and then the amplified signal is transferred to the subsequent stage within one clock period in a pipeline fashion. The dynamic preamplifiers consist of two stages. Each preamplifier stage is interpolated by a factor of 2, thus resulting in 4× interpolated preamplifiers for 6-bit flash ADC. Consequently, the prototype ADC achieves an SNDR of 32.97dB and SFDR of 41.52dB at 5.12 GS/s.

AB - As emerging applications require a high data-rate communication, ADCs for these systems should have a multi-GHz signal bandwidth [1]. Typically, a flash ADC is the most widely used structure for the GHz ADC thanks to 2N-1 comparators deployed in parallel for an N-bit operation. Flash ADCs usually adopt a track-and-hold (T/H) at the frontend to sample its high-speed inputs before the quantization, and thus the frontend T/H often limits the speed and resolution of the ADCs [1-4]. In addition, a dedicated time for the T/H should be compromised with comparators' operation time out of the given sampling period. This work presents a 6-bit 5.12 GS/s flash ADC with T/H-embedded dynamic preamplifier. Without having a dedicated T/H, the first preamplifiers sample the input signal at the output and then the amplified signal is transferred to the subsequent stage within one clock period in a pipeline fashion. The dynamic preamplifiers consist of two stages. Each preamplifier stage is interpolated by a factor of 2, thus resulting in 4× interpolated preamplifiers for 6-bit flash ADC. Consequently, the prototype ADC achieves an SNDR of 32.97dB and SFDR of 41.52dB at 5.12 GS/s.

UR - http://www.scopus.com/inward/record.url?scp=85146618245&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85146618245&partnerID=8YFLogxK

U2 - 10.1109/A-SSCC56115.2022.9980652

DO - 10.1109/A-SSCC56115.2022.9980652

M3 - Conference contribution

AN - SCOPUS:85146618245

T3 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings

BT - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022

Y2 - 6 November 2022 through 9 November 2022

ER -

Moon D, Lee S, Kim T, Choi WY , Chae Y. A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS. In 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2022. (2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings). doi: 10.1109/A-SSCC56115.2022.9980652

A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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