A 622-Mb/s mixed-mode BPSK demodulator using a half-rate bang-bang phase detector

Duho Kim, Kwang Chun Choi, Young Kwang Seo, Hyunchin Kim, Woo-Young Choi

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A new mixed-mode binary phase shift keying (BFSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications using already installed CATV lines. A prototype chip realized by 0.18-μm CMOS process can demodulate 622-Mb/s data at 1.4-GHz carrier frequency. At this data rate, the demodulator core consumes 27.5 mW from a 1.8 V power supply while the core chip area is 210 × 150 μm 2. The transmission over 20-m CATV line using the prototype chip is successfully demonstrated.

Original languageEnglish
Article number4639541
Pages (from-to)2284-2292
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number10
DOIs
Publication statusPublished - 2008 Oct 1

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Demodulators
Cable television systems
Detectors
Binary phase shift keying
Clocks
Recovery

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Kim, Duho ; Choi, Kwang Chun ; Seo, Young Kwang ; Kim, Hyunchin ; Choi, Woo-Young. / A 622-Mb/s mixed-mode BPSK demodulator using a half-rate bang-bang phase detector. In: IEEE Journal of Solid-State Circuits. 2008 ; Vol. 43, No. 10. pp. 2284-2292.
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A 622-Mb/s mixed-mode BPSK demodulator using a half-rate bang-bang phase detector. / Kim, Duho; Choi, Kwang Chun; Seo, Young Kwang; Kim, Hyunchin; Choi, Woo-Young.

In: IEEE Journal of Solid-State Circuits, Vol. 43, No. 10, 4639541, 01.10.2008, p. 2284-2292.

Research output: Contribution to journalArticle

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