A 622-Mb/s mixed-mode BPSK demodulator using a half-rate bang-bang phase detector

Duho Kim, Kwang Chun Choi, Young Kwang Seo, Hyunchin Kim, Woo Young Choi

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A new mixed-mode binary phase shift keying (BFSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications using already installed CATV lines. A prototype chip realized by 0.18-μm CMOS process can demodulate 622-Mb/s data at 1.4-GHz carrier frequency. At this data rate, the demodulator core consumes 27.5 mW from a 1.8 V power supply while the core chip area is 210 × 150 μm 2. The transmission over 20-m CATV line using the prototype chip is successfully demonstrated.

Original languageEnglish
Article number4639541
Pages (from-to)2284-2292
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number10
DOIs
Publication statusPublished - 2008 Oct

Bibliographical note

Funding Information:
Manuscript received August 11, 2007; revised June 17, 2008. Current version published October 8, 2008. This work was supported by “System IC 2010” project of Korea Ministry of Knowledge Economy and the IC Design Education Center (IDEC), Korea, and by Digital Solution Center of CTO, Samsung Electronics Co. Ltd.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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