A 622Mb/s BPSK demodulator with mixed-mode demodulation scheme

Duho Kim, Young Kwang Seo, Hyunchin Kim, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A new mixed-mode binary phase shift keying (BPSK) demodulator is demonstrated using a half-rate bangbang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications based on cable TV lines. A prototype chip is realized that can demodulate up to 622Mb/s data at 1.4GHz carrier frequency.

Original languageEnglish
Title of host publication2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages288-291
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
Duration: 2007 Nov 122007 Nov 14

Publication series

Name2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Other

Other2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
CountryKorea, Republic of
CityJeju
Period07/11/1207/11/14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 622Mb/s BPSK demodulator with mixed-mode demodulation scheme'. Together they form a unique fingerprint.

  • Cite this

    Kim, D., Seo, Y. K., Kim, H., & Choi, W. Y. (2007). A 622Mb/s BPSK demodulator with mixed-mode demodulation scheme. In 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 288-291). [4425687] (2007 IEEE Asian Solid-State Circuits Conference, A-SSCC). https://doi.org/10.1109/ASSCC.2007.4425687