A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme

Kang Yeob Park; Woo Young Choi; Seon Young Lee; Won Seok Oh

doi:10.1109/ISCAS.2012.6271589

A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme

Kang Yeob Park, Woo Young Choi, Seon Young Lee, Won Seok Oh

Department of Electrical and Electronic Engineering

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

In this paper, we report a 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme that can be used for long-haul optical transmission of various display standards. The serializer includes three clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers, and optical front-end circuits. To eliminate the need for a wide-range phase-locked loop, the fixed-data-rate scheme is used. The ASIC produces 6.24-Gb/s serialized data from parallel input signals and, with them, drives a vertical-cavity surface-emitting laser. The serializer ASIC occupies 3.45 mm2 and consumes 151.7 mW.

Original language	English
Pages	1704-1707
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271589
Publication status	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 2012 May 20 → 2012 May 23

Other

Other	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	12/5/20 → 12/5/23

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISCAS.2012.6271589

Cite this

@conference{adacac7ea8574071b6c7d763730bc034,

title = "A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme",

abstract = "In this paper, we report a 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme that can be used for long-haul optical transmission of various display standards. The serializer includes three clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers, and optical front-end circuits. To eliminate the need for a wide-range phase-locked loop, the fixed-data-rate scheme is used. The ASIC produces 6.24-Gb/s serialized data from parallel input signals and, with them, drives a vertical-cavity surface-emitting laser. The serializer ASIC occupies 3.45 mm2 and consumes 151.7 mW.",

author = "Park, {Kang Yeob} and Choi, {Woo Young} and Lee, {Seon Young} and Oh, {Won Seok}",

year = "2012",

doi = "10.1109/ISCAS.2012.6271589",

language = "English",

pages = "1704--1707",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

TY - CONF

T1 - A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme

AU - Park, Kang Yeob

AU - Choi, Woo Young

AU - Lee, Seon Young

AU - Oh, Won Seok

PY - 2012

Y1 - 2012

N2 - In this paper, we report a 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme that can be used for long-haul optical transmission of various display standards. The serializer includes three clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers, and optical front-end circuits. To eliminate the need for a wide-range phase-locked loop, the fixed-data-rate scheme is used. The ASIC produces 6.24-Gb/s serialized data from parallel input signals and, with them, drives a vertical-cavity surface-emitting laser. The serializer ASIC occupies 3.45 mm2 and consumes 151.7 mW.

AB - In this paper, we report a 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme that can be used for long-haul optical transmission of various display standards. The serializer includes three clock-and-data-recovery circuits, de-multiplexers, a digital processing block, a phase-locked-loop, multiplexers, and optical front-end circuits. To eliminate the need for a wide-range phase-locked loop, the fixed-data-rate scheme is used. The ASIC produces 6.24-Gb/s serialized data from parallel input signals and, with them, drives a vertical-cavity surface-emitting laser. The serializer ASIC occupies 3.45 mm2 and consumes 151.7 mW.

UR - http://www.scopus.com/inward/record.url?scp=84866626326&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866626326&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271589

DO - 10.1109/ISCAS.2012.6271589

M3 - Paper

AN - SCOPUS:84866626326

SP - 1704

EP - 1707

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme

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