A 6.3 μw 20 bit incremental zoom-ADC with 6 ppm INL and 1 μv offset

Youngcheol Chae; Kamran Souri; Kofi A.A. Makinwa

doi:10.1109/JSSC.2013.2278737

A 6.3 μw 20 bit incremental zoom-ADC with 6 ppm INL and 1 μv offset

Youngcheol Chae, Kamran Souri, Kofi A.A. Makinwa

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article

74 Citations (Scopus)

Abstract

A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm²; chip was fabricated in a standard 0.16 μm CMOS process.

Original language	English
Article number	6587137
Pages (from-to)	3019-3027
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	48
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2013.2278737
Publication status	Published - 2013 Dec 1

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/JSSC.2013.2278737

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Chae, Y., Souri, K., & Makinwa, K. A. A. (2013). A 6.3 μw 20 bit incremental zoom-ADC with 6 ppm INL and 1 μv offset. IEEE Journal of Solid-State Circuits, 48(12), 3019-3027. [6587137]. https://doi.org/10.1109/JSSC.2013.2278737

@article{5696815af16342c0b3c0dd239d69b915,

title = "A 6.3 μw 20 bit incremental zoom-ADC with 6 ppm INL and 1 μv offset",

abstract = "A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2; chip was fabricated in a standard 0.16 μm CMOS process.",

author = "Youngcheol Chae and Kamran Souri and Makinwa, {Kofi A.A.}",

year = "2013",

month = dec,

day = "1",

doi = "10.1109/JSSC.2013.2278737",

language = "English",

volume = "48",

pages = "3019--3027",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - A 6.3 μw 20 bit incremental zoom-ADC with 6 ppm INL and 1 μv offset

AU - Chae, Youngcheol

AU - Souri, Kamran

AU - Makinwa, Kofi A.A.

PY - 2013/12/1

Y1 - 2013/12/1

N2 - A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2; chip was fabricated in a standard 0.16 μm CMOS process.

AB - A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2; chip was fabricated in a standard 0.16 μm CMOS process.

UR - http://www.scopus.com/inward/record.url?scp=84889679725&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84889679725&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2013.2278737

DO - 10.1109/JSSC.2013.2278737

M3 - Article

AN - SCOPUS:84889679725

VL - 48

SP - 3019

EP - 3027

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 12

M1 - 6587137

ER -