A 6.3 μw 20 bit incremental zoom-ADC with 6 ppm INL and 1 μv offset

Youngcheol Chae, Kamran Souri, Kofi A.A. Makinwa

Research output: Contribution to journalArticle

69 Citations (Scopus)

Abstract

A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2; chip was fabricated in a standard 0.16 μm CMOS process.

Original languageEnglish
Article number6587137
Pages (from-to)3019-3027
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume48
Issue number12
DOIs
Publication statusPublished - 2013 Dec 1

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Error correction
Energy efficiency
Sensors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chae, Youngcheol ; Souri, Kamran ; Makinwa, Kofi A.A. / A 6.3 μw 20 bit incremental zoom-ADC with 6 ppm INL and 1 μv offset. In: IEEE Journal of Solid-State Circuits. 2013 ; Vol. 48, No. 12. pp. 3019-3027.
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A 6.3 μw 20 bit incremental zoom-ADC with 6 ppm INL and 1 μv offset. / Chae, Youngcheol; Souri, Kamran; Makinwa, Kofi A.A.

In: IEEE Journal of Solid-State Circuits, Vol. 48, No. 12, 6587137, 01.12.2013, p. 3019-3027.

Research output: Contribution to journalArticle

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