A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

C. H. Kim, J. H. Lee, J. B. Lee, B. S. Kim, C. S. Park, S. B. Lee, S. Y. Lee, C. W. Park, J. G. Roh, H. S. Nam, D. G. Kim, D. Y. Lee, T. S. Jung, H. Yoon, S. I. Cho

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Abstract

A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at Vcc = 3.3 V and T = 25°C. The circuit features are: 1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, 2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and 3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.

Original languageEnglish
Pages (from-to)1703-1709
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume33
Issue number11
DOIs
Publication statusPublished - 1998 Nov

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Kim, C. H., Lee, J. H., Lee, J. B., Kim, B. S., Park, C. S., Lee, S. B., Lee, S. Y., Park, C. W., Roh, J. G., Nam, H. S., Kim, D. G., Lee, D. Y., Jung, T. S., Yoon, H., & Cho, S. I. (1998). A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. IEEE Journal of Solid-State Circuits, 33(11), 1703-1709. https://doi.org/10.1109/4.726563