A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS

Continuous-rate referenceless clock and data recovery (CDR) circuits are capable of operating over a wide range of data rates in multiple standards. To achieve wide-range operation without an external reference clock, several frequency detection techniques are presented [1]-[5]. However, most of the previous techniques require considerable hardware and power overhead to obtain information for frequency detection. It leads to a performance tradeoff between capture range, lock time, and power consumption. As well as the performance aspects, they rarely address significant concerns such as compatibility with the conventional CDR architecture, transition from phase locking to frequency locking, and harmonic locking. In this work, a referenceless CDR employing a stochastic phase-frequency detection technique is proposed. While the proposed CDR architecture is almost similar to the conventional bang-bang CDR, it achieves an unlimited frequency detection capability by adopting a machine learning (ML)-inspired design procedure. The design procedure finds optimal weights for both phase and frequency detection utilizing the same information as the bang-bang phase detector (BBPD). As a result, the proposed technique achieves low-power, wide-range operation with minimal hardware overhead while overcoming the conventional logical approaches. Moreover, a robust operation without the transition and harmonic locking issues is obtained.