A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS

Jeongho Hwang; Hong Seok Choi; Hyungrok Do; Gyu Seob Jeong; Daehyun Koh; Kwanseo Park; Sungwoo Kim; Deog Kyoon Jeong

doi:10.23919/VLSIC.2019.8777952

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS

Jeongho Hwang, Hong Seok Choi, Hyungrok Do, Gyu Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm².

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C268-C269
ISBN (Electronic)	9784863487185
DOIs	https://doi.org/10.23919/VLSIC.2019.8777952
Publication status	Published - 2019 Jun
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 2019 Jun 9 → 2019 Jun 14

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2019-June

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/Territory	Japan
City	Kyoto
Period	19/6/9 → 19/6/14

Bibliographical note

Publisher Copyright:
© 2019 JSAP.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.23919/VLSIC.2019.8777952

Cite this

Hwang, J., Choi, H. S., Do, H., Jeong, G. S., Koh, D., Park, K., Kim, S., & Jeong, D. K. (2019). A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C268-C269). [8777952] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2019.8777952

@inproceedings{6b7aea217ec04908a84aa233f65676a0,

title = "A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS",

abstract = "This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm2.",

author = "Jeongho Hwang and Choi, {Hong Seok} and Hyungrok Do and Jeong, {Gyu Seob} and Daehyun Koh and Kwanseo Park and Sungwoo Kim and Jeong, {Deog Kyoon}",

note = "Publisher Copyright: {\textcopyright} 2019 JSAP.; 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

year = "2019",

month = jun,

doi = "10.23919/VLSIC.2019.8777952",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "C268--C269",

booktitle = "2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers",

address = "United States",

}

Hwang, J, Choi, HS, Do, H, Jeong, GS, Koh, D, Park, K, Kim, S & Jeong, DK 2019, A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8777952, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. C268-C269, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 19/6/9. https://doi.org/10.23919/VLSIC.2019.8777952

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS. / Hwang, Jeongho; Choi, Hong Seok; Do, Hyungrok et al.

2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. C268-C269 8777952 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS

AU - Hwang, Jeongho

AU - Choi, Hong Seok

AU - Do, Hyungrok

AU - Jeong, Gyu Seob

AU - Koh, Daehyun

AU - Park, Kwanseo

AU - Kim, Sungwoo

AU - Jeong, Deog Kyoon

PY - 2019/6

Y1 - 2019/6

N2 - This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm2.

AB - This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm2.

UR - http://www.scopus.com/inward/record.url?scp=85073898594&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85073898594&partnerID=8YFLogxK

U2 - 10.23919/VLSIC.2019.8777952

DO - 10.23919/VLSIC.2019.8777952

M3 - Conference contribution

AN - SCOPUS:85073898594

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C268-C269

BT - 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 33rd Symposium on VLSI Circuits, VLSI Circuits 2019

Y2 - 9 June 2019 through 14 June 2019

ER -

Hwang J, Choi HS, Do H, Jeong GS, Koh D, Park K et al. A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. C268-C269. 8777952. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2019.8777952

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS

Abstract

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Bibliographical note

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