A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter with 3-Tap Asymmetric FFE in 65nm CMOS

Jeongho Hwang, Hong Seok Choi, Hyungrok Do, Gyu Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog Kyoon Jeong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm2.

Original languageEnglish
Title of host publication2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC268-C269
ISBN (Electronic)9784863487185
DOIs
Publication statusPublished - 2019 Jun
Event33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan
Duration: 2019 Jun 92019 Jun 14

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2019-June

Conference

Conference33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/TerritoryJapan
CityKyoto
Period19/6/919/6/14

Bibliographical note

Publisher Copyright:
© 2019 JSAP.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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