A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR with Multi-Phase, Oversampling PFD in 65-nm CMOS

Kwanseo Park, Woorham Bae, Jinhyung Lee, Jeongho Hwang, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)

Abstract

A single-loop referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is proposed that tracks the frequency difference by detecting the drift direction of the non-return to zero bit stream with respect to the multi-phase clock and generates UP/DN output signals accordingly. When frequency locked, the BBPFD is degenerated into the conventional bang-bang phase detector (BBPD). The UP/DN output signals from the BBPFD are thus connected directly to the loop filter, thereby reducing the acquisition time without any loss of cycles. The effect of sampling phase mismatch is analyzed, and the capture range is calculated. In addition, the frequency acquisition time is analytically derived and verified by simulation. The proposed CDR has been implemented in a 65-nm CMOS process and occupies an active area of 0.047 mm2. The measured capture range is 6.7-11.2 Gb/s, and the frequency acquisition time is less than 2.19 μ The proposed CDR achieves error-free operation (BER < 10-12) for PRBS31 pattern and consumes 22.5 mW at 10 Gb/s.

Original languageEnglish
Article number8453909
Pages (from-to)2982-2993
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume53
Issue number10
DOIs
Publication statusPublished - 2018 Oct

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR with Multi-Phase, Oversampling PFD in 65-nm CMOS'. Together they form a unique fingerprint.

Cite this