A 7-GHz CMOS bidirectional variable gain amplifier with low gain and phase imbalances

Bosung Suh, Doojung Kim, Byung Wook Min

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

This paper presents a bidirectional variable gain amplifier (BVGA) with a low imbalance between amplification directions in 65-nm CMOS process. The BVGA is composed of two symmetric bidirectional amplifiers (BA) and a distributed attenuator (DA) for a low directional imbalance. The amplification direction is changed by the switching supply and ground voltages of a common gate amplifier in the BA. Switchable matching networks are designed with self-switching n-channel CMOS (NMOS) transistors in order to eliminate two single-pole-double-throw switches. The BVGA gain is controlled by the gate bias voltage of three NMOS varistors in the DA. Shunt inductors under the NMOS varistors are used to minimize the phase imbalance owing to the DA attenuation. The total chip size is 1848× 628μl {m}-{2} including pads. The gains of the BVGA are 2.3-11.5 dB and return loss is <-6 dB at 7 GHz. The 3-dB bandwidth of the BVGA is 2 GHz that is from 6 to 8 GHz. The measured output 1-dB power compression point and minimum noise figure are 4.6 dBm and 6.7 dB. The measured gain and phase directional imbalances are <0.1 dB and <4° in the C-band. The power consumption of the BVGA is 72.5 mW.

Original languageEnglish
Article number8293696
Pages (from-to)2669-2678
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume65
Issue number9
DOIs
Publication statusPublished - 2018 Sep

Bibliographical note

Funding Information:
Manuscript received September 8, 2017; revised December 15, 2017 and January 15, 2018; accepted January 30, 2018. Date of publication February 15, 2018; date of current version August 3, 2018. This paper was recommended by Associate Editor A. Worapishet. This work was supported by YSSRC and Space Core Technology Program through the National Research Foundation of Korea funded by the Ministry of Science and ICT (2017M1A3A3A02016255). The MPW was supported by IDEC. (Bosung Suh and Doojung Kim contributed equally to this work.) (Corresponding author: Byung-Wook Min.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, South Korea (e-mail: bmin@yonsei.ac.kr).

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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