This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm2 and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, re spectively.
|Title of host publication||2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2016 Jan 19|
|Event||11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China|
Duration: 2015 Nov 9 → 2015 Nov 11
|Name||2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings|
|Conference||11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015|
|Period||15/11/9 → 15/11/11|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering