A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

Woorham Bae, Haram Ju, Kwanseo Park, Sung Yong Cho, Deog Kyoon Jeong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm2 and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, re spectively.

Original languageEnglish
Title of host publication2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467371919
DOIs
Publication statusPublished - 2016 Jan 19
Event11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China
Duration: 2015 Nov 92015 Nov 11

Publication series

Name2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

Conference

Conference11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
Country/TerritoryChina
CityXiamen, Fujian
Period15/11/915/11/11

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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