A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

Woorham Bae; Haram Ju; Kwanseo Park; Sung Yong Cho; Deog Kyoon Jeong

doi:10.1109/ASSCC.2015.7387448

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

Woorham Bae, Haram Ju, Kwanseo Park, Sung Yong Cho, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm² and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, re spectively.

Original language	English
Title of host publication	2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467371919
DOIs	https://doi.org/10.1109/ASSCC.2015.7387448
Publication status	Published - 2016 Jan 19
Event	11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China Duration: 2015 Nov 9 → 2015 Nov 11

Publication series

Name	2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

Conference

Conference	11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
Country/Territory	China
City	Xiamen, Fujian
Period	15/11/9 → 15/11/11

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2015.7387448

Cite this

Bae, W., Ju, H., Park, K., Cho, S. Y., & Jeong, D. K. (2016). A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings [7387448] (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2015.7387448

Bae, Woorham ; Ju, Haram ; Park, Kwanseo et al. / A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings).

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title = "A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS",

abstract = "This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm2 and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, re spectively.",

author = "Woorham Bae and Haram Ju and Kwanseo Park and Cho, {Sung Yong} and Jeong, {Deog Kyoon}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 ; Conference date: 09-11-2015 Through 11-11-2015",

year = "2016",

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doi = "10.1109/ASSCC.2015.7387448",

language = "English",

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Bae, W, Ju, H, Park, K, Cho, SY & Jeong, DK 2016, A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. in 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings., 7387448, 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xiamen, Fujian, China, 15/11/9. https://doi.org/10.1109/ASSCC.2015.7387448

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. / Bae, Woorham; Ju, Haram; Park, Kwanseo et al.

2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. 7387448 (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

AU - Bae, Woorham

AU - Ju, Haram

AU - Park, Kwanseo

AU - Cho, Sung Yong

AU - Jeong, Deog Kyoon

PY - 2016/1/19

Y1 - 2016/1/19

N2 - This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm2 and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, re spectively.

AB - This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm2 and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, re spectively.

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M3 - Conference contribution

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T3 - 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

BT - 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015

Y2 - 9 November 2015 through 11 November 2015

ER -

Bae W, Ju H, Park K, Cho SY, Jeong DK. A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. 7387448. (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). doi: 10.1109/ASSCC.2015.7387448

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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