A 77-81GHz 3-Stage Transformer-Matched CMOS Power Amplifier

Deok Young Kim, Tae Wook Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The 77-81GHz power amplifier is designed using a 28nm CMOS process. The circuit is designed with cascode technique for a drive stage and neutralization technique for a power stage. Each stage consists of a matching network with transformer and inductors. The simulated maximum output power is 7.6 dBm, and the maximum power efficiency is 8%. The small signal gain at 77 GHz obtained from the simulation is 16.7 dB. The designed power amplifier of 1V of the supply power consumes 66mW of DC power.

Original languageEnglish
Title of host publication2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665408578
DOIs
Publication statusPublished - 2021
Event2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021 - Gangwon, Korea, Republic of
Duration: 2021 Nov 12021 Nov 3

Publication series

Name2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021

Conference

Conference2021 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2021
Country/TerritoryKorea, Republic of
CityGangwon
Period21/11/121/11/3

Bibliographical note

Funding Information:
This work was supported by Samsung Electronics Co. Ltd. (2020-11-1539). The CAD tool was supported by KAIST IDEC.

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

  • Instrumentation
  • Computer Networks and Communications
  • Signal Processing
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A 77-81GHz 3-Stage Transformer-Matched CMOS Power Amplifier'. Together they form a unique fingerprint.

Cite this