In this paper, a 90° phase-shift delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) is proposed. The proposed DLL increases the accuracies of the duty cycle and 90° phase shift by compensating PVT variation using a closed-loop DCC and a closed-loop 90° phase shift, and achieves a smaller area by reducing the delay-line length by 25% to 50% as compared to conventional DLLs with the DCC and/or 90° phase shift. We also propose a 90° phase detector consisting of a time-to-voltage converter and a sense amplifier to independently control and lock the DCC and 90° phase-shift loops. The proposed DLL is designed using the 0.13 μm process technology with a 1.2 V supply voltage. The operating frequency range is from 400 MHz to 800 MHz. Monte Carlo simulation results show that the output duty cycle error ranges from -0.21% to 0.22% for an input duty cycle range of 30% to 70%, and the 90° phase-shift error is less than 1.66°, which is lower than a 5.7ps error at 800 MHz. Finally, the power consumption of the proposed DLL is 2.8 mW at 800 MHz.
Bibliographical noteFunding Information:
1This work was supported by the IT R&D program of MKE/KEIT [10034834, a development of ASIC chip for next generation high speed ATE].
All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering