A 90 phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface

Dong Hoon Jung, Kyung Ho Ryu, Seong Ook Jung

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

In this paper, a 90° phase-shift delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) is proposed. The proposed DLL increases the accuracies of the duty cycle and 90° phase shift by compensating PVT variation using a closed-loop DCC and a closed-loop 90° phase shift, and achieves a smaller area by reducing the delay-line length by 25% to 50% as compared to conventional DLLs with the DCC and/or 90° phase shift. We also propose a 90° phase detector consisting of a time-to-voltage converter and a sense amplifier to independently control and lock the DCC and 90° phase-shift loops. The proposed DLL is designed using the 0.13 μm process technology with a 1.2 V supply voltage. The operating frequency range is from 400 MHz to 800 MHz. Monte Carlo simulation results show that the output duty cycle error ranges from -0.21% to 0.22% for an input duty cycle range of 30% to 70%, and the 90° phase-shift error is less than 1.66°, which is lower than a 5.7ps error at 800 MHz. Finally, the power consumption of the proposed DLL is 2.8 mW at 800 MHz.

Original languageEnglish
Article number5681119
Pages (from-to)2400-2405
Number of pages6
JournalIEEE Transactions on Consumer Electronics
Volume56
Issue number4
DOIs
Publication statusPublished - 2010 Nov 1

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Dynamic random access storage
Phase shift
Electric delay lines
Electric potential
Electric power utilization
Detectors

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Electrical and Electronic Engineering

Cite this

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abstract = "In this paper, a 90° phase-shift delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) is proposed. The proposed DLL increases the accuracies of the duty cycle and 90° phase shift by compensating PVT variation using a closed-loop DCC and a closed-loop 90° phase shift, and achieves a smaller area by reducing the delay-line length by 25{\%} to 50{\%} as compared to conventional DLLs with the DCC and/or 90° phase shift. We also propose a 90° phase detector consisting of a time-to-voltage converter and a sense amplifier to independently control and lock the DCC and 90° phase-shift loops. The proposed DLL is designed using the 0.13 μm process technology with a 1.2 V supply voltage. The operating frequency range is from 400 MHz to 800 MHz. Monte Carlo simulation results show that the output duty cycle error ranges from -0.21{\%} to 0.22{\%} for an input duty cycle range of 30{\%} to 70{\%}, and the 90° phase-shift error is less than 1.66°, which is lower than a 5.7ps error at 800 MHz. Finally, the power consumption of the proposed DLL is 2.8 mW at 800 MHz.",
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A 90 phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface. / Jung, Dong Hoon; Ryu, Kyung Ho; Jung, Seong Ook.

In: IEEE Transactions on Consumer Electronics, Vol. 56, No. 4, 5681119, 01.11.2010, p. 2400-2405.

Research output: Contribution to journalArticle

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