A low-power 1.6-GHz phase-locked loop (PLL) based on a novel supply-regulated voltage-controlled oscillator (SR-VCO) including an active-loop filter (ALF) is realized. In this PLL, an active $RC$ filter is combined with SR-VCO, achieving the advantages of ALF PLL without penalties in power consumption or phase noises. The PLL has measured rms jitter of 4.82 ps, and its core consumes 990 μW from 1-V supply while the chip area is 420 × 570μm2 including on-chip passive components required for the ALF and the supply regulator.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2013|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering