A banked-promotion translation lookaside buffer system

Jung Hoon Lee, Seh Woong Jeong, Shin-Dug Kim, Charles Weems

Research output: Contribution to journalArticle

Abstract

We present a simple but high performance translation lookaside buffer (TLB) system with low power consumption for use in embedded systems. Our TLB structure supports two page sizes dynamically and selectively to achieve high performance with low hardware cost. To minimize power consumption, a banked-TLB is constructed by dividing one fully associative (FA) TLB space into two separate FA TLBs. These two structures are integrated to form a banked-promotion (BP) TLB. Promotion overcomes the unbalanced utilization of a banked-TLB by moving adjacent entries out of the primary banks into a separate super-page TLB. Simulation results show that the Energy*Delay product can be reduced by about 99.8%, 19.2%, 24.2%, and 24.4% compared with a FA TLB, a micro-TLB, a banked-TLB, and a victim-TLB respectively. Therefore, the BP TLB offers high performance with low power consumption and low hardware cost.

Original languageEnglish
Pages (from-to)1065-1078
Number of pages14
JournalJournal of Systems Architecture
Volume47
Issue number14-15
DOIs
Publication statusPublished - 2002 Aug 1

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Electric power utilization
Hardware
Embedded systems
Costs

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

Cite this

Lee, Jung Hoon ; Jeong, Seh Woong ; Kim, Shin-Dug ; Weems, Charles. / A banked-promotion translation lookaside buffer system. In: Journal of Systems Architecture. 2002 ; Vol. 47, No. 14-15. pp. 1065-1078.
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A banked-promotion translation lookaside buffer system. / Lee, Jung Hoon; Jeong, Seh Woong; Kim, Shin-Dug; Weems, Charles.

In: Journal of Systems Architecture, Vol. 47, No. 14-15, 01.08.2002, p. 1065-1078.

Research output: Contribution to journalArticle

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