A BIRA using fault-free memory region for area reduction

Chang Hyun Oh, Sae Eun Kim, Joon Sung Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

As memory capacity and density grow, the test cost and yield improvement of embedded memories have become more crucial. For embedded memories, BIRA (built-in redundancy analysis) is widely used to improve yield. BIRA replaces faulty cells with spare cells. BIRA requires an extra hardware overhead since it needs to store and analyze faults. The most important factor in BIRA is the reduction of area overhead while keeping very high repair rate. Most of previous studies on BIRA utilize CAMs (content-addressable memories) for storing faulty memory addresses. The area overhead for CAM is not negligible, hence, a CAM is shared by many memory blocks to perform a repair process. With this BIRA architecture, each memory block needs to be analyzed one by one. This makes the CAM a bottleneck of improvement for area overhead and analysis speed in BIRA. In order to improve area overhead and analysis speed, we propose a BIRA architecture and RA (redundancy analysis) algorithm using a fault-free region in embedded memory instead of deploying extra CAMs. The proposed RA algorithm stores faulty cell addresses in the fault-free region and achieves a very high repair rate. The proposed BIRA brings a significant area reduction. In addition, it allows a parallel memory test by using its own memory instead of shared CAMs.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages480-482
Number of pages3
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 252016 Oct 28

Publication series

Name2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16/10/2516/10/28

Bibliographical note

Funding Information:
This work was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education (NRF- 2015R1D1A1A01058856)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing

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