A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor

Dae Hyun Kwon, Young Seok Park, Woo Young Choi

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be programmed by scanning the dead-zone width of a variable dead-zone BBPD in the time domain. Its linear-like gain characteristics result in less sensitive CDR performance against input jitter and process, voltage, and temperature (PVT) variations. In addition, a built-in on-chip jitter monitor can be easily implemented using our ML-BBPD. A prototype 1.25-Gb/s CDR based on our ML-BBPD with a built-in jitter monitor is realized with 0.18-μ m CMOS technology and its performance is successfully verified with measurement.

Original languageEnglish
Article number7112583
Pages (from-to)1472-1480
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume62
Issue number6
DOIs
Publication statusPublished - 2015 Jun 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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