A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

A. Lattuca, G. Mazza, G. Aglieri Rinella, C. Cavicchioli, N. Chanlek, A. Collu, Y. Degerli, A. Dorokhov, C. Flouzat, D. Gajanana, C. Gao, F. Guilloux, H. Hillemanns, S. Hristozkov, A. Junique, M. Keil, D. Kim, M. Kofarago, T. Kugathasan, Youngil Kwon & 18 others M. Mager, K. Marek Sielewicz, C. Augusto Marin Tobon, D. Marras, P. Martinengo, H. Mugnier, L. Musa, T. Hung Pham, C. Puggioni, F. Reidt, P. Riedler, J. Rousset, S. Siddhanta, W. Snoeys, M. Song, G. Usai, J. Willem Van Hoorne, P. Yang

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

Original languageEnglish
Article numberC01066
JournalJournal of Instrumentation
Volume11
Issue number1
DOIs
Publication statusPublished - 2016 Jan 26

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multipliers
data transmission
Tracking System
Phase locked loops
Data Transmission
Data communication systems
clocks
Multiplier
Driver
Clocks
CMOS
High Speed
Chip
chips
high speed
Pixels
Networks (circuits)
Pixel
pixels
Digital to analog conversion

All Science Journal Classification (ASJC) codes

  • Instrumentation
  • Mathematical Physics

Cite this

Lattuca, A. ; Mazza, G. ; Rinella, G. Aglieri ; Cavicchioli, C. ; Chanlek, N. ; Collu, A. ; Degerli, Y. ; Dorokhov, A. ; Flouzat, C. ; Gajanana, D. ; Gao, C. ; Guilloux, F. ; Hillemanns, H. ; Hristozkov, S. ; Junique, A. ; Keil, M. ; Kim, D. ; Kofarago, M. ; Kugathasan, T. ; Kwon, Youngil ; Mager, M. ; Sielewicz, K. Marek ; Tobon, C. Augusto Marin ; Marras, D. ; Martinengo, P. ; Mugnier, H. ; Musa, L. ; Pham, T. Hung ; Puggioni, C. ; Reidt, F. ; Riedler, P. ; Rousset, J. ; Siddhanta, S. ; Snoeys, W. ; Song, M. ; Usai, G. ; Van Hoorne, J. Willem ; Yang, P. / A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip. In: Journal of Instrumentation. 2016 ; Vol. 11, No. 1.
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title = "A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip",
abstract = "This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.",
author = "A. Lattuca and G. Mazza and Rinella, {G. Aglieri} and C. Cavicchioli and N. Chanlek and A. Collu and Y. Degerli and A. Dorokhov and C. Flouzat and D. Gajanana and C. Gao and F. Guilloux and H. Hillemanns and S. Hristozkov and A. Junique and M. Keil and D. Kim and M. Kofarago and T. Kugathasan and Youngil Kwon and M. Mager and Sielewicz, {K. Marek} and Tobon, {C. Augusto Marin} and D. Marras and P. Martinengo and H. Mugnier and L. Musa and Pham, {T. Hung} and C. Puggioni and F. Reidt and P. Riedler and J. Rousset and S. Siddhanta and W. Snoeys and M. Song and G. Usai and {Van Hoorne}, {J. Willem} and P. Yang",
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Lattuca, A, Mazza, G, Rinella, GA, Cavicchioli, C, Chanlek, N, Collu, A, Degerli, Y, Dorokhov, A, Flouzat, C, Gajanana, D, Gao, C, Guilloux, F, Hillemanns, H, Hristozkov, S, Junique, A, Keil, M, Kim, D, Kofarago, M, Kugathasan, T, Kwon, Y, Mager, M, Sielewicz, KM, Tobon, CAM, Marras, D, Martinengo, P, Mugnier, H, Musa, L, Pham, TH, Puggioni, C, Reidt, F, Riedler, P, Rousset, J, Siddhanta, S, Snoeys, W, Song, M, Usai, G, Van Hoorne, JW & Yang, P 2016, 'A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip', Journal of Instrumentation, vol. 11, no. 1, C01066. https://doi.org/10.1088/1748-0221/11/01/C01066

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip. / Lattuca, A.; Mazza, G.; Rinella, G. Aglieri; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Youngil; Mager, M.; Sielewicz, K. Marek; Tobon, C. Augusto Marin; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

In: Journal of Instrumentation, Vol. 11, No. 1, C01066, 26.01.2016.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

AU - Lattuca, A.

AU - Mazza, G.

AU - Rinella, G. Aglieri

AU - Cavicchioli, C.

AU - Chanlek, N.

AU - Collu, A.

AU - Degerli, Y.

AU - Dorokhov, A.

AU - Flouzat, C.

AU - Gajanana, D.

AU - Gao, C.

AU - Guilloux, F.

AU - Hillemanns, H.

AU - Hristozkov, S.

AU - Junique, A.

AU - Keil, M.

AU - Kim, D.

AU - Kofarago, M.

AU - Kugathasan, T.

AU - Kwon, Youngil

AU - Mager, M.

AU - Sielewicz, K. Marek

AU - Tobon, C. Augusto Marin

AU - Marras, D.

AU - Martinengo, P.

AU - Mugnier, H.

AU - Musa, L.

AU - Pham, T. Hung

AU - Puggioni, C.

AU - Reidt, F.

AU - Riedler, P.

AU - Rousset, J.

AU - Siddhanta, S.

AU - Snoeys, W.

AU - Song, M.

AU - Usai, G.

AU - Van Hoorne, J. Willem

AU - Yang, P.

PY - 2016/1/26

Y1 - 2016/1/26

N2 - This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

AB - This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

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UR - http://www.scopus.com/inward/citedby.url?scp=84957019909&partnerID=8YFLogxK

U2 - 10.1088/1748-0221/11/01/C01066

DO - 10.1088/1748-0221/11/01/C01066

M3 - Article

VL - 11

JO - Journal of Instrumentation

JF - Journal of Instrumentation

SN - 1748-0221

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M1 - C01066

ER -