A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

A. Lattuca, G. Mazza, G. Aglieri Rinella, C. Cavicchioli, N. Chanlek, A. Collu, Y. Degerli, A. Dorokhov, C. Flouzat, D. Gajanana, C. Gao, F. Guilloux, H. Hillemanns, S. Hristozkov, A. Junique, M. Keil, D. Kim, M. Kofarago, T. Kugathasan, Y. KwonM. Mager, K. Marek Sielewicz, C. Augusto Marin Tobon, D. Marras, P. Martinengo, H. Mugnier, L. Musa, T. Hung Pham, C. Puggioni, F. Reidt, P. Riedler, J. Rousset, S. Siddhanta, W. Snoeys, M. Song, G. Usai, J. Willem Van Hoorne, P. Yang

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Abstract

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

Original languageEnglish
Article numberC01066
JournalJournal of Instrumentation
Volume11
Issue number1
DOIs
Publication statusPublished - 2016 Jan 26

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All Science Journal Classification (ASJC) codes

  • Mathematical Physics
  • Instrumentation

Cite this

Lattuca, A., Mazza, G., Rinella, G. A., Cavicchioli, C., Chanlek, N., Collu, A., Degerli, Y., Dorokhov, A., Flouzat, C., Gajanana, D., Gao, C., Guilloux, F., Hillemanns, H., Hristozkov, S., Junique, A., Keil, M., Kim, D., Kofarago, M., Kugathasan, T., ... Yang, P. (2016). A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip. Journal of Instrumentation, 11(1), [C01066]. https://doi.org/10.1088/1748-0221/11/01/C01066