A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

A. Lattuca, G. Mazza, G. Aglieri Rinella, C. Cavicchioli, N. Chanlek, A. Collu, Y. Degerli, A. Dorokhov, C. Flouzat, D. Gajanana, C. Gao, F. Guilloux, H. Hillemanns, S. Hristozkov, A. Junique, M. Keil, D. Kim, M. Kofarago, T. Kugathasan, Y. KwonM. Mager, K. Marek Sielewicz, C. Augusto Marin Tobon, D. Marras, P. Martinengo, H. Mugnier, L. Musa, T. Hung Pham, C. Puggioni, F. Reidt, P. Riedler, J. Rousset, S. Siddhanta, W. Snoeys, M. Song, G. Usai, J. Willem Van Hoorne, P. Yang

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