A CMOS image sensor with reset level control using dynamic reset current source for noise suppression

Kwang Hyun Lee, Euisik Yoon

Research output: Contribution to journalConference article

7 Citations (Scopus)

Abstract

A 512 × 384 CMOS image sensor in 0.18μm 1P4M technology with 5.9μm pixel pitch and a dynamic reset current source to compensate for kTC reset noise and fixed pattern noise is presented. A total of 390μV(rms) readout noise, and a factor of two improvement over conventional reset is achieved. The chip operates at 1.8V and consumes 40mW excluding I/O and off-chip DAC for a single-slope ADC at 24frames/s.

Original languageEnglish
Pages (from-to)114-115+107+516
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume47
Publication statusPublished - 2004 Jun 2
EventDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
Duration: 2003 Feb 152003 Feb 19

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Level control
Image sensors
Pixels

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

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title = "A CMOS image sensor with reset level control using dynamic reset current source for noise suppression",
abstract = "A 512 × 384 CMOS image sensor in 0.18μm 1P4M technology with 5.9μm pixel pitch and a dynamic reset current source to compensate for kTC reset noise and fixed pattern noise is presented. A total of 390μV(rms) readout noise, and a factor of two improvement over conventional reset is achieved. The chip operates at 1.8V and consumes 40mW excluding I/O and off-chip DAC for a single-slope ADC at 24frames/s.",
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N2 - A 512 × 384 CMOS image sensor in 0.18μm 1P4M technology with 5.9μm pixel pitch and a dynamic reset current source to compensate for kTC reset noise and fixed pattern noise is presented. A total of 390μV(rms) readout noise, and a factor of two improvement over conventional reset is achieved. The chip operates at 1.8V and consumes 40mW excluding I/O and off-chip DAC for a single-slope ADC at 24frames/s.

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