# A Compact 3-30-GHz 68.5-ps CMOS True-Time Delay for Wideband Phased Array Systems

Minjae Jung, Byung Wook Min

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1 Citation (Scopus)

## Abstract

This article presents a compact 4-bit switched-line true-time delay (TTD) circuit over a wide frequency range extending from 3 to 30 GHz using novel delay elements. The delay elements, namely, the cascading coupled all-pass network (CAPN) and noncoupled all-pass network (NCAPN), were employed in the proposed TTD circuit to improve the delay-bandwidth product (DBW) while maintaining its compact size and low delay variation (DV). For comparison, a theoretical analysis for understanding the group delay feature of the APN with various coupling coefficients is presented along with low-pass network (LPN). To verify the proposed structure, the proposed delays are applied to construct the 4-bit switched-line TTD by utilizing two single-pole double-through (SPDT) and three double-pole double-through (DPDT) switches in a 28-nm CMOS process. The circuit has a compact size of 1.7 mm $\times0.2$ mm, with a maximum delay of 68.5 ps and a minimum delay of 4.6 ps. The measured average insertion loss is 13.5 dB, and the in/out return loss is better than 10 dB across 3-30 GHz. The measured rms delay and gain errors are less than 2 ps and 3.2 dB, respectively, over the operating frequency range. To the best of our knowledge, the proposed TTD achieves the largest figure of merit (FoM) among the integrated TTD circuits.

Original language English 9204450 5371-5380 10 IEEE Transactions on Microwave Theory and Techniques 68 12 https://doi.org/10.1109/TMTT.2020.3023710 Published - 2020 Dec

### Bibliographical note

Funding Information:
Manuscript received January 10, 2020; revised May 2, 2020, July 8, 2020, and August 10, 2020; accepted August 17, 2020. Date of publication September 22, 2020; date of current version December 3, 2020. This work was supported in part by the Yonsei-Samsung Strategy Research Center and in part by the Institute for Information & Communications Technology Planning & Evaluation (IITP) Grant funded by the Korean Government (MSIT) under Grant 2020000218. The EDA tool was supported by the IC Design Education Center. (Corresponding author: Byung-Wook Min.) Minjae Jung was with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea. He is now with the Network Business, Samsung Electronics, Suwon 16677, South Korea (e-mail: minjae3716@gmail.com).