A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer

J. H. Yum, H. S. Shin, Ryan M. Mushinski, Todd W. Hudnall, J. Oh, W. Y. Loh, C. W. Bielawski, G. Bersuker, S. K. Banerjee, W. E. Wang, P. D. Kirsch, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Extending our previous study demonstrating that ALD-BeO hi-k on Si and III-V exhibits excellent electrical characteristics, we discuss the advantages of using BeO as the interface passivation layer (IPL) in silicon metal-oxide-semiconductor field effect transistors (Si-MOSFETs) from the perspective of the gate-first and the gate-last process. By comparing three hi-k stacks, BeO/HfO2, Al2O3/HfO2, and SiO2/HfO2, fabricated using the gate first and gate last processes, we demonstrate that for both processes, BeO/HfO2 significantly outperforms the other stacks in terms of drive current, transconductance (Gm), subthreshold swing (SS), inversion capacitance, and mobility.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
DOIs
Publication statusPublished - 2013
Event2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 - Hsinchu, Taiwan, Province of China
Duration: 2013 Apr 222013 Apr 24

Publication series

Name2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

Other

Other2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
CountryTaiwan, Province of China
CityHsinchu
Period13/4/2213/4/24

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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