A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer

J. H. Yum; H. S. Shin; Ryan M. Mushinski; Todd W. Hudnall; J. Oh; W. Y. Loh; C. W. Bielawski; G. Bersuker; S. K. Banerjee; W. E. Wang; P. D. Kirsch; R. Jammy

doi:10.1109/VLSI-TSA.2013.6545611

A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer

J. H. Yum, H. S. Shin, Ryan M. Mushinski, Todd W. Hudnall, J. Oh, W. Y. Loh, C. W. Bielawski, G. Bersuker, S. K. Banerjee, W. E. Wang, P. D. Kirsch, R. Jammy

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Extending our previous study demonstrating that ALD-BeO hi-k on Si and III-V exhibits excellent electrical characteristics, we discuss the advantages of using BeO as the interface passivation layer (IPL) in silicon metal-oxide-semiconductor field effect transistors (Si-MOSFETs) from the perspective of the gate-first and the gate-last process. By comparing three hi-k stacks, BeO/HfO₂, Al₂O₃/HfO₂, and SiO₂/HfO₂, fabricated using the gate first and gate last processes, we demonstrate that for both processes, BeO/HfO₂ significantly outperforms the other stacks in terms of drive current, transconductance (G_m), subthreshold swing (SS), inversion capacitance, and mobility.

Original language	English
Title of host publication	2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
DOIs	https://doi.org/10.1109/VLSI-TSA.2013.6545611
Publication status	Published - 2013
Event	2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 - Hsinchu, Taiwan, Province of China Duration: 2013 Apr 22 → 2013 Apr 24

Publication series

Name	2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

Other

Other	2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	13/4/22 → 13/4/24

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/VLSI-TSA.2013.6545611

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Yum, J. H., Shin, H. S., Mushinski, R. M., Hudnall, T. W., Oh, J., Loh, W. Y., Bielawski, C. W., Bersuker, G., Banerjee, S. K., Wang, W. E., Kirsch, P. D., & Jammy, R. (2013). A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer. In 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 [6545611] (2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013). https://doi.org/10.1109/VLSI-TSA.2013.6545611

Yum, J. H. ; Shin, H. S. ; Mushinski, Ryan M. et al. / A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer. 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013. 2013. (2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013).

@inproceedings{eda3ce8b45ce4fb9a2c90975bd24ff08,

title = "A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer",

abstract = "Extending our previous study demonstrating that ALD-BeO hi-k on Si and III-V exhibits excellent electrical characteristics, we discuss the advantages of using BeO as the interface passivation layer (IPL) in silicon metal-oxide-semiconductor field effect transistors (Si-MOSFETs) from the perspective of the gate-first and the gate-last process. By comparing three hi-k stacks, BeO/HfO2, Al2O3/HfO2, and SiO2/HfO2, fabricated using the gate first and gate last processes, we demonstrate that for both processes, BeO/HfO2 significantly outperforms the other stacks in terms of drive current, transconductance (Gm), subthreshold swing (SS), inversion capacitance, and mobility.",

author = "Yum, {J. H.} and Shin, {H. S.} and Mushinski, {Ryan M.} and Hudnall, {Todd W.} and J. Oh and Loh, {W. Y.} and Bielawski, {C. W.} and G. Bersuker and Banerjee, {S. K.} and Wang, {W. E.} and Kirsch, {P. D.} and R. Jammy",

year = "2013",

doi = "10.1109/VLSI-TSA.2013.6545611",

language = "English",

isbn = "9781467330817",

series = "2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013",

booktitle = "2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013",

note = "2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 ; Conference date: 22-04-2013 Through 24-04-2013",

}

Yum, JH, Shin, HS, Mushinski, RM, Hudnall, TW, Oh, J, Loh, WY, Bielawski, CW, Bersuker, G, Banerjee, SK, Wang, WE, Kirsch, PD & Jammy, R 2013, A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer. in 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013., 6545611, 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013, 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013, Hsinchu, Taiwan, Province of China, 13/4/22. https://doi.org/10.1109/VLSI-TSA.2013.6545611

A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer. / Yum, J. H.; Shin, H. S.; Mushinski, Ryan M. et al.

2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013. 2013. 6545611 (2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer

AU - Yum, J. H.

AU - Shin, H. S.

AU - Mushinski, Ryan M.

AU - Hudnall, Todd W.

AU - Oh, J.

AU - Loh, W. Y.

AU - Bielawski, C. W.

AU - Bersuker, G.

AU - Banerjee, S. K.

AU - Wang, W. E.

AU - Kirsch, P. D.

AU - Jammy, R.

PY - 2013

Y1 - 2013

N2 - Extending our previous study demonstrating that ALD-BeO hi-k on Si and III-V exhibits excellent electrical characteristics, we discuss the advantages of using BeO as the interface passivation layer (IPL) in silicon metal-oxide-semiconductor field effect transistors (Si-MOSFETs) from the perspective of the gate-first and the gate-last process. By comparing three hi-k stacks, BeO/HfO2, Al2O3/HfO2, and SiO2/HfO2, fabricated using the gate first and gate last processes, we demonstrate that for both processes, BeO/HfO2 significantly outperforms the other stacks in terms of drive current, transconductance (Gm), subthreshold swing (SS), inversion capacitance, and mobility.

AB - Extending our previous study demonstrating that ALD-BeO hi-k on Si and III-V exhibits excellent electrical characteristics, we discuss the advantages of using BeO as the interface passivation layer (IPL) in silicon metal-oxide-semiconductor field effect transistors (Si-MOSFETs) from the perspective of the gate-first and the gate-last process. By comparing three hi-k stacks, BeO/HfO2, Al2O3/HfO2, and SiO2/HfO2, fabricated using the gate first and gate last processes, we demonstrate that for both processes, BeO/HfO2 significantly outperforms the other stacks in terms of drive current, transconductance (Gm), subthreshold swing (SS), inversion capacitance, and mobility.

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U2 - 10.1109/VLSI-TSA.2013.6545611

DO - 10.1109/VLSI-TSA.2013.6545611

M3 - Conference contribution

AN - SCOPUS:84881126638

SN - 9781467330817

T3 - 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

BT - 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

T2 - 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

Y2 - 22 April 2013 through 24 April 2013

ER -

Yum JH, Shin HS, Mushinski RM, Hudnall TW, Oh J, Loh WY et al. A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer. In 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013. 2013. 6545611. (2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013). doi: 10.1109/VLSI-TSA.2013.6545611

A comparative study of gate first and last Si MOSFETs fabrication processes using ALD beryllium oxide as an interface passivation layer

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