TY - GEN
T1 - A cost-effective demosaicked image enhancement for a single chip CMOS image sensor
AU - Lee, Wonjae
AU - Kim, Jaeseok
PY - 2005
Y1 - 2005
N2 - A cost-effective demosaicked image enhancement method for a single chip CMOS (Complementary Metal Oxide Semiconductor) image sensor which has on-chip ISP (Image Signal Processor) is introduced. CMOS image sensors are becoming popular, because various circuits can be integrated with it into a single chip. In a single chip CMOS image sensor for handheld devices which requires low power consumption, ISP has to be implemented to small size while maintaining the high performance. Demosaicking and image enhancing are the largest blocks in the ISP, because they need some line memories. In this paper, we propose a new method to minimize the number of line memory. In the proposed method, contrast enhancement is done using the buffered data for demosaicking. The green channel is used instead of luminance. Experimental results indicate that the proposed approach enhances the image quality without additional line memories. The proposed method is implemented on FPGA chip in real time mode, and performed successfully.
AB - A cost-effective demosaicked image enhancement method for a single chip CMOS (Complementary Metal Oxide Semiconductor) image sensor which has on-chip ISP (Image Signal Processor) is introduced. CMOS image sensors are becoming popular, because various circuits can be integrated with it into a single chip. In a single chip CMOS image sensor for handheld devices which requires low power consumption, ISP has to be implemented to small size while maintaining the high performance. Demosaicking and image enhancing are the largest blocks in the ISP, because they need some line memories. In this paper, we propose a new method to minimize the number of line memory. In the proposed method, contrast enhancement is done using the buffered data for demosaicking. The green channel is used instead of luminance. Experimental results indicate that the proposed approach enhances the image quality without additional line memories. The proposed method is implemented on FPGA chip in real time mode, and performed successfully.
UR - http://www.scopus.com/inward/record.url?scp=33846983525&partnerID=8YFLogxK
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U2 - 10.1109/SIPS.2005.1579855
DO - 10.1109/SIPS.2005.1579855
M3 - Conference contribution
AN - SCOPUS:33846983525
SN - 0780393341
SN - 9780780393349
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 148
EP - 153
BT - SiPS 2005
T2 - SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation
Y2 - 2 November 2005 through 4 November 2005
ER -