While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.
Bibliographical noteFunding Information:
This research was supported by the MOTIE (Ministry of Trade, Industry & Energy) (10067813) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.
© 2018 Choi et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
All Science Journal Classification (ASJC) codes
- Biochemistry, Genetics and Molecular Biology(all)
- Agricultural and Biological Sciences(all)