A debug scheme to improve the error identification in post-silicon validation

Inhyuk Choi, Won Jung, Hyunggoy Oh, Sungho Kang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

Original languageEnglish
Article numbere0202216
JournalPloS one
Volume13
Issue number9
DOIs
Publication statusPublished - 2018 Sep 1

Fingerprint

Silicon
silicon
semiconductors
Semiconductors
manufacturing
testing
Semiconductor materials
Testing

All Science Journal Classification (ASJC) codes

  • Biochemistry, Genetics and Molecular Biology(all)
  • Agricultural and Biological Sciences(all)

Cite this

Choi, Inhyuk ; Jung, Won ; Oh, Hyunggoy ; Kang, Sungho. / A debug scheme to improve the error identification in post-silicon validation. In: PloS one. 2018 ; Vol. 13, No. 9.
@article{973b6f15c5c24cb78f8bee6f10504cca,
title = "A debug scheme to improve the error identification in post-silicon validation",
abstract = "While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.",
author = "Inhyuk Choi and Won Jung and Hyunggoy Oh and Sungho Kang",
year = "2018",
month = "9",
day = "1",
doi = "10.1371/journal.pone.0202216",
language = "English",
volume = "13",
journal = "PLoS One",
issn = "1932-6203",
publisher = "Public Library of Science",
number = "9",

}

A debug scheme to improve the error identification in post-silicon validation. / Choi, Inhyuk; Jung, Won; Oh, Hyunggoy; Kang, Sungho.

In: PloS one, Vol. 13, No. 9, e0202216, 01.09.2018.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A debug scheme to improve the error identification in post-silicon validation

AU - Choi, Inhyuk

AU - Jung, Won

AU - Oh, Hyunggoy

AU - Kang, Sungho

PY - 2018/9/1

Y1 - 2018/9/1

N2 - While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

AB - While developing semiconductors, post-silicon validation is an important step to identify the errors that are not detected during the pre-silicon verification and manufacturing testing phases. When the design complexity increases, the required debug time also increases because additional debug data are required to identify the errors. In this study, we present a debug scheme that improves the error identification capability. The proposed debug approach concurrently generates three types of signatures using hierarchical multiple-input signature registers (MISRs). The error-suspect debug cycles are determined by analyzing the debug cycles that are commonly contained in the erroneous signatures of the three MISRs. To reduce the amount of debug data, we compare the high-level MISR signatures in real time with the golden signatures; further, we handle the remaining two MISRs based on the tag bits that are obtained from the results of the high-level MISR. The experimental results prove that the proposed debug structure can significantly improve the error identification capability using less debug data than that used in previous debug structure.

UR - http://www.scopus.com/inward/record.url?scp=85053025721&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85053025721&partnerID=8YFLogxK

U2 - 10.1371/journal.pone.0202216

DO - 10.1371/journal.pone.0202216

M3 - Article

VL - 13

JO - PLoS One

JF - PLoS One

SN - 1932-6203

IS - 9

M1 - e0202216

ER -