A decoder for short BCH codes with high decoding efficiency and low power for emerging memories

Sara Choi, Hong Keun Ahn, Byung Kyu Song, Jung Pill Kim, Seung H. Kang, Seong Ook Jung

Research output: Contribution to journalArticle

Abstract

In this paper, a double-error-correcting and triple-error-detecting (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects the number of errors in a codeword immediately after syndrome generation and applies a different error correction algorithm depending on the error conditions. With the adaptive error correction technique, the average decoding latency and power consumption are significantly reduced owing to the increased decoding efficiency. To further reduce the power consumption, an invalid-transition-inhibition technique is proposed to remove the invalid transitions caused by glitches of syndrome vectors in the error-finding block. Synthesis results with an industry-compatible 65-nm technology library show that the proposed decoders for the (79, 64, 6) BCH code take only 37%-48% average decoding latency and achieve more than 70% power reduction compared to the conventional fully parallel decoder under the 10-4-10-2 raw bit-error rate.

Original languageEnglish
Article number8548588
Pages (from-to)387-397
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume27
Issue number2
DOIs
Publication statusPublished - 2019 Feb

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Decoding
Data storage equipment
Error correction
Electric power utilization
Bit error rate
Industry

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Choi, Sara ; Ahn, Hong Keun ; Song, Byung Kyu ; Kim, Jung Pill ; Kang, Seung H. ; Jung, Seong Ook. / A decoder for short BCH codes with high decoding efficiency and low power for emerging memories. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2019 ; Vol. 27, No. 2. pp. 387-397.
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A decoder for short BCH codes with high decoding efficiency and low power for emerging memories. / Choi, Sara; Ahn, Hong Keun; Song, Byung Kyu; Kim, Jung Pill; Kang, Seung H.; Jung, Seong Ook.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 2, 8548588, 02.2019, p. 387-397.

Research output: Contribution to journalArticle

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