Abstract
In this paper, a double-error-correcting and triple-error-detecting (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects the number of errors in a codeword immediately after syndrome generation and applies a different error correction algorithm depending on the error conditions. With the adaptive error correction technique, the average decoding latency and power consumption are significantly reduced owing to the increased decoding efficiency. To further reduce the power consumption, an invalid-transition-inhibition technique is proposed to remove the invalid transitions caused by glitches of syndrome vectors in the error-finding block. Synthesis results with an industry-compatible 65-nm technology library show that the proposed decoders for the (79, 64, 6) BCH code take only 37%-48% average decoding latency and achieve more than 70% power reduction compared to the conventional fully parallel decoder under the 10-4-10-2 raw bit-error rate.
| Original language | English |
|---|---|
| Article number | 8548588 |
| Pages (from-to) | 387-397 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 27 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2019 Feb |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
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A decoder for short BCH codes with high decoding efficiency and low power for emerging memories. / Choi, Sara; Ahn, Hong Keun; Song, Byung Kyu; Kim, Jung Pill; Kang, Seung H.; Jung, Seong Ook.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 2, 8548588, 02.2019, p. 387-397.Research output: Contribution to journal › Article
TY - JOUR
T1 - A decoder for short BCH codes with high decoding efficiency and low power for emerging memories
AU - Choi, Sara
AU - Ahn, Hong Keun
AU - Song, Byung Kyu
AU - Kim, Jung Pill
AU - Kang, Seung H.
AU - Jung, Seong Ook
PY - 2019/2
Y1 - 2019/2
N2 - In this paper, a double-error-correcting and triple-error-detecting (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects the number of errors in a codeword immediately after syndrome generation and applies a different error correction algorithm depending on the error conditions. With the adaptive error correction technique, the average decoding latency and power consumption are significantly reduced owing to the increased decoding efficiency. To further reduce the power consumption, an invalid-transition-inhibition technique is proposed to remove the invalid transitions caused by glitches of syndrome vectors in the error-finding block. Synthesis results with an industry-compatible 65-nm technology library show that the proposed decoders for the (79, 64, 6) BCH code take only 37%-48% average decoding latency and achieve more than 70% power reduction compared to the conventional fully parallel decoder under the 10-4-10-2 raw bit-error rate.
AB - In this paper, a double-error-correcting and triple-error-detecting (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects the number of errors in a codeword immediately after syndrome generation and applies a different error correction algorithm depending on the error conditions. With the adaptive error correction technique, the average decoding latency and power consumption are significantly reduced owing to the increased decoding efficiency. To further reduce the power consumption, an invalid-transition-inhibition technique is proposed to remove the invalid transitions caused by glitches of syndrome vectors in the error-finding block. Synthesis results with an industry-compatible 65-nm technology library show that the proposed decoders for the (79, 64, 6) BCH code take only 37%-48% average decoding latency and achieve more than 70% power reduction compared to the conventional fully parallel decoder under the 10-4-10-2 raw bit-error rate.
UR - http://www.scopus.com/inward/record.url?scp=85057824067&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85057824067&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2018.2877147
DO - 10.1109/TVLSI.2018.2877147
M3 - Article
AN - SCOPUS:85057824067
VL - 27
SP - 387
EP - 397
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 2
M1 - 8548588
ER -