A design of fast searcher for CDMA WLL system

Yongkwon Cho, Seongjoo Lee, Jaeseok Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We present a high-speed power-efficient fast searcher module for an initial code acquisition in CDMA wireless local loop (WLL) system. We introduce a double-dwell serial search algorithm with 16 parallel active correlators to meet mean code acquisition time required in WLL system. We pipeline parallel active correlators and make use of a common energy processing element and a microcontroller I/F block. As a result, hardware complexity is reduced to only 1/4 of a conventional searcher consisting of 16 correlators.

Original languageEnglish
Title of host publicationICVC 1999 - 6th International Conference on VLSI and CAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages582-585
Number of pages4
ISBN (Print)0780357272, 9780780357273
DOIs
Publication statusPublished - 1999
Event6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of
Duration: 1999 Oct 261999 Oct 27

Publication series

NameICVC 1999 - 6th International Conference on VLSI and CAD

Other

Other6th International Conference on VLSI and CAD, ICVC 1999
CountryKorea, Republic of
CitySeoul
Period99/10/2699/10/27

Bibliographical note

Funding Information:
This study was supported by the academic research fund of Ministry of Education, Republic of Korea, through Inter-University Semiconductor Research Center (ISRC 97-E-2039) in Seoul National University

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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