A deterministic way-prediction scheme using power-aware replacement policy

Jung Wook Park, Gi Ho Park, Sung Bae Park, Shin-Dug Kim

Research output: Contribution to journalArticle

Abstract

This research is to design a low power set-associative cache for embedded processors without additional delay or performance degradation. For this goal, deterministic way selection logic with power-aware replacement policy is designed to enable only one way of set-associative cache as in the direct-mapped cache. Delay analysis shows that the cache access time is almost the same as that of conventional set associative cache with additional way selection logic. Proposed architecture exploits the trade-offs between power and performance to achieve power reduction with the least performance loss. As the result of those approaches, simulation shows that the proposed architecture can reduce unit accessing power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.

Original languageEnglish
Pages (from-to)209-215
Number of pages7
JournalMicroprocessors and Microsystems
Volume30
Issue number4
DOIs
Publication statusPublished - 2006 Jun 6

Fingerprint

Electric power utilization
Degradation

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Park, Jung Wook ; Park, Gi Ho ; Park, Sung Bae ; Kim, Shin-Dug. / A deterministic way-prediction scheme using power-aware replacement policy. In: Microprocessors and Microsystems. 2006 ; Vol. 30, No. 4. pp. 209-215.
@article{a87aa4afc26c40b88befe5d8eaa80bac,
title = "A deterministic way-prediction scheme using power-aware replacement policy",
abstract = "This research is to design a low power set-associative cache for embedded processors without additional delay or performance degradation. For this goal, deterministic way selection logic with power-aware replacement policy is designed to enable only one way of set-associative cache as in the direct-mapped cache. Delay analysis shows that the cache access time is almost the same as that of conventional set associative cache with additional way selection logic. Proposed architecture exploits the trade-offs between power and performance to achieve power reduction with the least performance loss. As the result of those approaches, simulation shows that the proposed architecture can reduce unit accessing power consumption by 59{\%} over conventional set-associative caches with average 0.06{\%} of negligible performance loss.",
author = "Park, {Jung Wook} and Park, {Gi Ho} and Park, {Sung Bae} and Shin-Dug Kim",
year = "2006",
month = "6",
day = "6",
doi = "10.1016/j.micpro.2005.12.003",
language = "English",
volume = "30",
pages = "209--215",
journal = "Microprocessors and Microsystems",
issn = "0141-9331",
publisher = "Elsevier",
number = "4",

}

A deterministic way-prediction scheme using power-aware replacement policy. / Park, Jung Wook; Park, Gi Ho; Park, Sung Bae; Kim, Shin-Dug.

In: Microprocessors and Microsystems, Vol. 30, No. 4, 06.06.2006, p. 209-215.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A deterministic way-prediction scheme using power-aware replacement policy

AU - Park, Jung Wook

AU - Park, Gi Ho

AU - Park, Sung Bae

AU - Kim, Shin-Dug

PY - 2006/6/6

Y1 - 2006/6/6

N2 - This research is to design a low power set-associative cache for embedded processors without additional delay or performance degradation. For this goal, deterministic way selection logic with power-aware replacement policy is designed to enable only one way of set-associative cache as in the direct-mapped cache. Delay analysis shows that the cache access time is almost the same as that of conventional set associative cache with additional way selection logic. Proposed architecture exploits the trade-offs between power and performance to achieve power reduction with the least performance loss. As the result of those approaches, simulation shows that the proposed architecture can reduce unit accessing power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.

AB - This research is to design a low power set-associative cache for embedded processors without additional delay or performance degradation. For this goal, deterministic way selection logic with power-aware replacement policy is designed to enable only one way of set-associative cache as in the direct-mapped cache. Delay analysis shows that the cache access time is almost the same as that of conventional set associative cache with additional way selection logic. Proposed architecture exploits the trade-offs between power and performance to achieve power reduction with the least performance loss. As the result of those approaches, simulation shows that the proposed architecture can reduce unit accessing power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.

UR - http://www.scopus.com/inward/record.url?scp=33646880187&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646880187&partnerID=8YFLogxK

U2 - 10.1016/j.micpro.2005.12.003

DO - 10.1016/j.micpro.2005.12.003

M3 - Article

AN - SCOPUS:33646880187

VL - 30

SP - 209

EP - 215

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

IS - 4

ER -