A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

Kyuseung Han, Jae Jin Lee, Woojoo Lee, Jinho Lee

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y. Ogras, Arizona State University

Original languageEnglish
Article number8594625
Pages (from-to)81-87
Number of pages7
JournalIEEE Design and Test
Volume36
Issue number2
DOIs
Publication statusPublished - 2019 Apr

Bibliographical note

Funding Information:
This work was supported in part by the ICT R&D Program of MSIT/IITP (2018-0-00197, Development of ultra-low power intelligent edge system-on-chip technology based on lightweight RISC-V processor), and in part by NRF of Korea funded by the Ministry of Education (2017R1D1A1B03027911).

Publisher Copyright:
© 2013 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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