A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties

Kyuseung Han, Jae Jin Lee, Woojoo Lee, Jinho Lee

Research output: Contribution to journalArticle

Abstract

Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y. Ogras, Arizona State University

Original languageEnglish
Article number8594625
Pages (from-to)81-87
Number of pages7
JournalIEEE Design and Test
Volume36
Issue number2
DOIs
Publication statusPublished - 2019 Apr

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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